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Propagate debug loc info through prologue/epilogue.
[oota-llvm.git]
/
lib
/
CodeGen
/
RegAllocBigBlock.cpp
diff --git
a/lib/CodeGen/RegAllocBigBlock.cpp
b/lib/CodeGen/RegAllocBigBlock.cpp
index 38fb5e6894d10198020a77b25cd0a7acd343f72b..91e4099d0c45761fea7ca9849b6d062d2984104b 100644
(file)
--- a/
lib/CodeGen/RegAllocBigBlock.cpp
+++ b/
lib/CodeGen/RegAllocBigBlock.cpp
@@
-52,11
+52,11
@@
STATISTIC(NumStores, "Number of stores added");
STATISTIC(NumLoads , "Number of loads added");
STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
STATISTIC(NumLoads , "Number of loads added");
STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
-namespace {
- static RegisterRegAlloc
- bigBlockRegAlloc("bigblock", " Big-block register allocator",
- createBigBlockRegisterAllocator);
+static RegisterRegAlloc
+ bigBlockRegAlloc("bigblock", "Big-block register allocator",
+ createBigBlockRegisterAllocator);
+namespace {
/// VRegKeyInfo - Defines magic values required to use VirtRegs as DenseMap
/// keys.
struct VRegKeyInfo {
/// VRegKeyInfo - Defines magic values required to use VirtRegs as DenseMap
/// keys.
struct VRegKeyInfo {
@@
-82,7
+82,7
@@
namespace {
class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass {
public:
static char ID;
class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass {
public:
static char ID;
- RABigBlock() : MachineFunctionPass(
(intptr_t)
&ID) {}
+ RABigBlock() : MachineFunctionPass(&ID) {}
private:
/// TM - For getting at TargetMachine info
///
private:
/// TM - For getting at TargetMachine info
///
@@
-385,7
+385,7
@@
bool RABigBlock::isPhysRegAvailable(unsigned PhysReg) const {
// not free!
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
*AliasSet; ++AliasSet)
// not free!
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
*AliasSet; ++AliasSet)
- if (PhysRegsUsed[*AliasSet]
!= -1
) // Aliased register in use?
+ if (PhysRegsUsed[*AliasSet]
>= 0
) // Aliased register in use?
return false; // Can't use this reg then.
return true;
}
return false; // Can't use this reg then.
return true;
}
@@
-518,7
+518,7
@@
MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
assignVirtToPhysReg(VirtReg, PhysReg);
} else { // no free registers available.
// try to fold the spill into the instruction
assignVirtToPhysReg(VirtReg, PhysReg);
} else { // no free registers available.
// try to fold the spill into the instruction
- SmallVector<unsigned,
2
> Ops;
+ SmallVector<unsigned,
1
> Ops;
Ops.push_back(OpNum);
if(MachineInstr* FMI = TII->foldMemoryOperand(*MF, MI, Ops, FrameIndex)) {
++NumFolded;
Ops.push_back(OpNum);
if(MachineInstr* FMI = TII->foldMemoryOperand(*MF, MI, Ops, FrameIndex)) {
++NumFolded;
@@
-560,7
+560,7
@@
void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) {
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// look for vreg reads..
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// look for vreg reads..
- if (MO.isReg
ister
() && !MO.isDef() && MO.getReg() &&
+ if (MO.isReg() && !MO.isDef() && MO.getReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
// ..and add them to the read table.
VRegTimes* &Times = VRegReadTable[MO.getReg()];
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
// ..and add them to the read table.
VRegTimes* &Times = VRegReadTable[MO.getReg()];
@@
-589,7
+589,7
@@
void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) {
static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isReg
ister
() && MO.getReg() == Reg && MO.isImplicit() &&
+ if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
MO.isDef() && !MO.isDead())
return true;
}
MO.isDef() && !MO.isDead())
return true;
}
@@
-601,7
+601,7
@@
static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isReg
ister
() && MO.getReg() == Reg && MO.isImplicit() &&
+ if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
!MO.isDef() && MO.isKill())
return true;
}
!MO.isDef() && MO.isKill())
return true;
}
@@
-653,7
+653,7
@@
void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
SmallVector<unsigned, 8> Kills;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
SmallVector<unsigned, 8> Kills;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isReg
ister
() && MO.isKill()) {
+ if (MO.isReg() && MO.isKill()) {
if (!MO.isImplicit())
Kills.push_back(MO.getReg());
else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
if (!MO.isImplicit())
Kills.push_back(MO.getReg());
else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
@@
-673,7
+673,7
@@
void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// here we are looking for only used operands (never def&use)
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// here we are looking for only used operands (never def&use)
- if (MO.isReg
ister
() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
+ if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
@@
-719,7
+719,7
@@
void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
// are defined, and marking explicit destinations in the PhysRegsUsed map.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
// are defined, and marking explicit destinations in the PhysRegsUsed map.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isReg
ister
() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
+ if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
@@
-764,7
+764,7
@@
void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
SmallVector<unsigned, 8> DeadDefs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
SmallVector<unsigned, 8> DeadDefs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isReg
ister
() && MO.isDead())
+ if (MO.isReg() && MO.isDead())
DeadDefs.push_back(MO.getReg());
}
DeadDefs.push_back(MO.getReg());
}
@@
-775,7
+775,7
@@
void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isReg
ister
() && MO.isDef() && MO.getReg() &&
+ if (MO.isReg() && MO.isDef() && MO.getReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
@@
-808,14
+808,14
@@
void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (PhysReg) {
DOUT << " Register " << RegInfo->getName(PhysReg)
<< " [%reg" << VirtReg
if (PhysReg) {
DOUT << " Register " << RegInfo->getName(PhysReg)
<< " [%reg" << VirtReg
- << "] is never used, removing it fr
ame live lis
t\n";
+ << "] is never used, removing it fr
om live se
t\n";
removePhysReg(PhysReg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DOUT << " Register " << RegInfo->getName(*AliasSet)
<< " [%reg" << *AliasSet
removePhysReg(PhysReg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DOUT << " Register " << RegInfo->getName(*AliasSet)
<< " [%reg" << *AliasSet
- << "] is never used, removing it fr
ame live lis
t\n";
+ << "] is never used, removing it fr
om live se
t\n";
removePhysReg(*AliasSet);
}
}
removePhysReg(*AliasSet);
}
}
@@
-823,8
+823,9
@@
void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
// Finally, if this is a noop copy instruction, zap it.
}
// Finally, if this is a noop copy instruction, zap it.
- unsigned SrcReg, DstReg;
- if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+ if (TII.isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
+ SrcReg == DstReg)
MBB.erase(MI);
}
MBB.erase(MI);
}