projects
/
oota-llvm.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
More constification of things. More comments added. No functionality
[oota-llvm.git]
/
lib
/
CodeGen
/
RegAllocLinearScan.cpp
diff --git
a/lib/CodeGen/RegAllocLinearScan.cpp
b/lib/CodeGen/RegAllocLinearScan.cpp
index ad9c5ec051981615232e5b31053684a7fad8d872..c70ff9524328d237e0eb48f85cc097c3446c1c22 100644
(file)
--- a/
lib/CodeGen/RegAllocLinearScan.cpp
+++ b/
lib/CodeGen/RegAllocLinearScan.cpp
@@
-2,8
+2,8
@@
//
// The LLVM Compiler Infrastructure
//
//
// The LLVM Compiler Infrastructure
//
-// This file
was developed by the LLVM research group and is distributed under
-//
the University of Illinois Open Source
License. See LICENSE.TXT for details.
+// This file
is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
//
@@
-16,14
+16,14
@@
#include "PhysRegTracker.h"
#include "VirtRegMap.h"
#include "llvm/Function.h"
#include "PhysRegTracker.h"
#include "VirtRegMap.h"
#include "llvm/Function.h"
-#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterCoalescer.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterCoalescer.h"
-#include "llvm/CodeGen/SSARegMap.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/EquivalenceClasses.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/EquivalenceClasses.h"
@@
-62,12
+62,12
@@
namespace {
MachineFunction* mf_;
const TargetMachine* tm_;
MachineFunction* mf_;
const TargetMachine* tm_;
- const
MRegisterInfo* m
ri_;
+ const
TargetRegisterInfo* t
ri_;
const TargetInstrInfo* tii_;
const TargetInstrInfo* tii_;
-
SSARegMap *regmap
_;
+
MachineRegisterInfo *reginfo
_;
BitVector allocatableRegs_;
LiveIntervals* li_;
BitVector allocatableRegs_;
LiveIntervals* li_;
- const LoopInfo *loopInfo;
+ const
Machine
LoopInfo *loopInfo;
/// handled_ - Intervals are added to the handled_ set in the order of their
/// start value. This is uses for backtracking.
/// handled_ - Intervals are added to the handled_ set in the order of their
/// start value. This is uses for backtracking.
@@
-103,7
+103,9
@@
namespace {
// Make sure PassManager knows which analyses to make available
// to coalescing and which analyses coalescing invalidates.
AU.addRequiredTransitive<RegisterCoalescer>();
// Make sure PassManager knows which analyses to make available
// to coalescing and which analyses coalescing invalidates.
AU.addRequiredTransitive<RegisterCoalescer>();
- AU.addRequired<LoopInfo>();
+ AU.addRequired<MachineLoopInfo>();
+ AU.addPreserved<MachineLoopInfo>();
+ AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU);
}
MachineFunctionPass::getAnalysisUsage(AU);
}
@@
-159,10
+161,10
@@
namespace {
for (; i != e; ++i) {
DOUT << "\t" << *i->first << " -> ";
unsigned reg = i->first->reg;
for (; i != e; ++i) {
DOUT << "\t" << *i->first << " -> ";
unsigned reg = i->first->reg;
- if (
M
RegisterInfo::isVirtualRegister(reg)) {
+ if (
Target
RegisterInfo::isVirtualRegister(reg)) {
reg = vrm_->getPhys(reg);
}
reg = vrm_->getPhys(reg);
}
- DOUT <<
m
ri_->getName(reg) << '\n';
+ DOUT <<
t
ri_->getName(reg) << '\n';
}
}
};
}
}
};
@@
-170,17
+172,17
@@
namespace {
}
void RALinScan::ComputeRelatedRegClasses() {
}
void RALinScan::ComputeRelatedRegClasses() {
- const
MRegisterInfo &MRI = *m
ri_;
+ const
TargetRegisterInfo &TRI = *t
ri_;
// First pass, add all reg classes to the union, and determine at least one
// reg class that each register is in.
bool HasAliases = false;
// First pass, add all reg classes to the union, and determine at least one
// reg class that each register is in.
bool HasAliases = false;
- for (
MRegisterInfo::regclass_iterator RCI = M
RI.regclass_begin(),
- E =
M
RI.regclass_end(); RCI != E; ++RCI) {
+ for (
TargetRegisterInfo::regclass_iterator RCI = T
RI.regclass_begin(),
+ E =
T
RI.regclass_end(); RCI != E; ++RCI) {
RelatedRegClasses.insert(*RCI);
for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
I != E; ++I) {
RelatedRegClasses.insert(*RCI);
for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
I != E; ++I) {
- HasAliases = HasAliases || *
M
RI.getAliasSet(*I) != 0;
+ HasAliases = HasAliases || *
T
RI.getAliasSet(*I) != 0;
const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
if (PRC) {
const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
if (PRC) {
@@
-200,7
+202,7
@@
void RALinScan::ComputeRelatedRegClasses() {
for (std::map<unsigned, const TargetRegisterClass*>::iterator
I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
I != E; ++I)
for (std::map<unsigned, const TargetRegisterClass*>::iterator
I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
I != E; ++I)
- for (const unsigned *AS =
M
RI.getAliasSet(I->first); *AS; ++AS)
+ for (const unsigned *AS =
T
RI.getAliasSet(I->first); *AS; ++AS)
RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
}
RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
}
@@
-222,7
+224,7
@@
unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
unsigned SrcReg, DstReg;
if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
return Reg;
unsigned SrcReg, DstReg;
if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
return Reg;
- if (
M
RegisterInfo::isVirtualRegister(SrcReg))
+ if (
Target
RegisterInfo::isVirtualRegister(SrcReg))
if (!vrm_->isAssignedReg(SrcReg))
return Reg;
else
if (!vrm_->isAssignedReg(SrcReg))
return Reg;
else
@@
-230,13
+232,13
@@
unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
if (Reg == SrcReg)
return Reg;
if (Reg == SrcReg)
return Reg;
- const TargetRegisterClass *RC = reg
map
_->getRegClass(cur.reg);
+ const TargetRegisterClass *RC = reg
info
_->getRegClass(cur.reg);
if (!RC->contains(SrcReg))
return Reg;
// Try to coalesce.
if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
if (!RC->contains(SrcReg))
return Reg;
// Try to coalesce.
if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
- DOUT << "Coalescing: " << cur << " -> " <<
m
ri_->getName(SrcReg) << '\n';
+ DOUT << "Coalescing: " << cur << " -> " <<
t
ri_->getName(SrcReg) << '\n';
vrm_->clearVirt(cur.reg);
vrm_->assignVirt2Phys(cur.reg, SrcReg);
++NumCoalesce;
vrm_->clearVirt(cur.reg);
vrm_->assignVirt2Phys(cur.reg, SrcReg);
++NumCoalesce;
@@
-249,12
+251,12
@@
unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn;
tm_ = &fn.getTarget();
bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn;
tm_ = &fn.getTarget();
-
m
ri_ = tm_->getRegisterInfo();
+
t
ri_ = tm_->getRegisterInfo();
tii_ = tm_->getInstrInfo();
tii_ = tm_->getInstrInfo();
- reg
map_ = mf_->getSSARegMap
();
- allocatableRegs_ =
m
ri_->getAllocatableSet(fn);
+ reg
info_ = &mf_->getRegInfo
();
+ allocatableRegs_ =
t
ri_->getAllocatableSet(fn);
li_ = &getAnalysis<LiveIntervals>();
li_ = &getAnalysis<LiveIntervals>();
- loopInfo = &getAnalysis<LoopInfo>();
+ loopInfo = &getAnalysis<
Machine
LoopInfo>();
// We don't run the coalescer here because we have no reason to
// interact with it. If the coalescer requires interaction, it
// We don't run the coalescer here because we have no reason to
// interact with it. If the coalescer requires interaction, it
@@
-265,7
+267,7
@@
bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
if (RelatedRegClasses.empty())
ComputeRelatedRegClasses();
if (RelatedRegClasses.empty())
ComputeRelatedRegClasses();
- if (!prt_.get()) prt_.reset(new PhysRegTracker(*
m
ri_));
+ if (!prt_.get()) prt_.reset(new PhysRegTracker(*
t
ri_));
vrm_.reset(new VirtRegMap(*mf_));
if (!spiller_.get()) spiller_.reset(createSpiller());
vrm_.reset(new VirtRegMap(*mf_));
if (!spiller_.get()) spiller_.reset(createSpiller());
@@
-295,8
+297,8
@@
void RALinScan::initIntervalSets()
"interval sets should be empty on initialization");
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
"interval sets should be empty on initialization");
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
- if (
M
RegisterInfo::isPhysicalRegister(i->second.reg)) {
-
mf
_->setPhysRegUsed(i->second.reg);
+ if (
Target
RegisterInfo::isPhysicalRegister(i->second.reg)) {
+
reginfo
_->setPhysRegUsed(i->second.reg);
fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
} else
unhandled_.push(&i->second);
fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
} else
unhandled_.push(&i->second);
@@
-321,7
+323,7
@@
void RALinScan::linearScan()
processActiveIntervals(cur->beginNumber());
processInactiveIntervals(cur->beginNumber());
processActiveIntervals(cur->beginNumber());
processInactiveIntervals(cur->beginNumber());
- assert(
M
RegisterInfo::isVirtualRegister(cur->reg) &&
+ assert(
Target
RegisterInfo::isVirtualRegister(cur->reg) &&
"Can only allocate virtual registers!");
// Allocating a virtual register. try to find a free
"Can only allocate virtual registers!");
// Allocating a virtual register. try to find a free
@@
-338,7
+340,7
@@
void RALinScan::linearScan()
IntervalPtr &IP = active_.back();
unsigned reg = IP.first->reg;
DOUT << "\tinterval " << *IP.first << " expired\n";
IntervalPtr &IP = active_.back();
unsigned reg = IP.first->reg;
DOUT << "\tinterval " << *IP.first << " expired\n";
- assert(
M
RegisterInfo::isVirtualRegister(reg) &&
+ assert(
Target
RegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
@@
-357,7
+359,7
@@
void RALinScan::linearScan()
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
LiveInterval &cur = i->second;
unsigned Reg = 0;
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
LiveInterval &cur = i->second;
unsigned Reg = 0;
- bool isPhys =
M
RegisterInfo::isPhysicalRegister(cur.reg);
+ bool isPhys =
Target
RegisterInfo::isPhysicalRegister(cur.reg);
if (isPhys)
Reg = i->second.reg;
else if (vrm_->isAssignedReg(cur.reg))
if (isPhys)
Reg = i->second.reg;
else if (vrm_->isAssignedReg(cur.reg))
@@
-397,7
+399,7
@@
void RALinScan::processActiveIntervals(unsigned CurPoint)
if (IntervalPos == Interval->end()) { // Remove expired intervals.
DOUT << "\t\tinterval " << *Interval << " expired\n";
if (IntervalPos == Interval->end()) { // Remove expired intervals.
DOUT << "\t\tinterval " << *Interval << " expired\n";
- assert(
M
RegisterInfo::isVirtualRegister(reg) &&
+ assert(
Target
RegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
@@
-410,7
+412,7
@@
void RALinScan::processActiveIntervals(unsigned CurPoint)
} else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list.
DOUT << "\t\tinterval " << *Interval << " inactive\n";
} else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list.
DOUT << "\t\tinterval " << *Interval << " inactive\n";
- assert(
M
RegisterInfo::isVirtualRegister(reg) &&
+ assert(
Target
RegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
@@
-451,7
+453,7
@@
void RALinScan::processInactiveIntervals(unsigned CurPoint)
} else if (IntervalPos->start <= CurPoint) {
// move re-activated intervals in active list
DOUT << "\t\tinterval " << *Interval << " active\n";
} else if (IntervalPos->start <= CurPoint) {
// move re-activated intervals in active list
DOUT << "\t\tinterval " << *Interval << " active\n";
- assert(
M
RegisterInfo::isVirtualRegister(reg) &&
+ assert(
Target
RegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->addRegUse(reg);
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->addRegUse(reg);
@@
-473,9
+475,9
@@
void RALinScan::processInactiveIntervals(unsigned CurPoint)
/// register and its weight.
static void updateSpillWeights(std::vector<float> &Weights,
unsigned reg, float weight,
/// register and its weight.
static void updateSpillWeights(std::vector<float> &Weights,
unsigned reg, float weight,
- const
MRegisterInfo *M
RI) {
+ const
TargetRegisterInfo *T
RI) {
Weights[reg] += weight;
Weights[reg] += weight;
- for (const unsigned* as =
M
RI->getAliasSet(reg); *as; ++as)
+ for (const unsigned* as =
T
RI->getAliasSet(reg); *as; ++as)
Weights[*as] += weight;
}
Weights[*as] += weight;
}
@@
-508,7
+510,7
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
unsigned StartPosition = cur->beginNumber();
std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
unsigned StartPosition = cur->beginNumber();
- const TargetRegisterClass *RC = reg
map
_->getRegClass(cur->reg);
+ const TargetRegisterClass *RC = reg
info
_->getRegClass(cur->reg);
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
// If this live interval is defined by a move instruction and its source is
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
// If this live interval is defined by a move instruction and its source is
@@
-523,7
+525,7
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
unsigned SrcReg, DstReg;
if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
unsigned Reg = 0;
unsigned SrcReg, DstReg;
if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
unsigned Reg = 0;
- if (
M
RegisterInfo::isPhysicalRegister(SrcReg))
+ if (
Target
RegisterInfo::isPhysicalRegister(SrcReg))
Reg = SrcReg;
else if (vrm_->isAssignedReg(SrcReg))
Reg = vrm_->getPhys(SrcReg);
Reg = SrcReg;
else if (vrm_->isAssignedReg(SrcReg))
Reg = vrm_->getPhys(SrcReg);
@@
-538,9
+540,9
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
for (IntervalPtrs::const_iterator i = inactive_.begin(),
e = inactive_.end(); i != e; ++i) {
unsigned Reg = i->first->reg;
for (IntervalPtrs::const_iterator i = inactive_.begin(),
e = inactive_.end(); i != e; ++i) {
unsigned Reg = i->first->reg;
- assert(
M
RegisterInfo::isVirtualRegister(Reg) &&
+ assert(
Target
RegisterInfo::isVirtualRegister(Reg) &&
"Can only allocate virtual registers!");
"Can only allocate virtual registers!");
- const TargetRegisterClass *RegRC = reg
map
_->getRegClass(Reg);
+ const TargetRegisterClass *RegRC = reg
info
_->getRegClass(Reg);
// If this is not in a related reg class to the register we're allocating,
// don't check it.
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
// If this is not in a related reg class to the register we're allocating,
// don't check it.
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
@@
-562,7
+564,7
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
// conflict with it. Check to see if we conflict with it or any of its
// aliases.
SmallSet<unsigned, 8> RegAliases;
// conflict with it. Check to see if we conflict with it or any of its
// aliases.
SmallSet<unsigned, 8> RegAliases;
- for (const unsigned *AS =
m
ri_->getAliasSet(physReg); *AS; ++AS)
+ for (const unsigned *AS =
t
ri_->getAliasSet(physReg); *AS; ++AS)
RegAliases.insert(*AS);
bool ConflictsWithFixed = false;
RegAliases.insert(*AS);
bool ConflictsWithFixed = false;
@@
-624,7
+626,7
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
// the free physical register and add this interval to the active
// list.
if (physReg) {
// the free physical register and add this interval to the active
// list.
if (physReg) {
- DOUT <<
m
ri_->getName(physReg) << '\n';
+ DOUT <<
t
ri_->getName(physReg) << '\n';
vrm_->assignVirt2Phys(cur->reg, physReg);
prt_->addRegUse(physReg);
active_.push_back(std::make_pair(cur, cur->begin()));
vrm_->assignVirt2Phys(cur->reg, physReg);
prt_->addRegUse(physReg);
active_.push_back(std::make_pair(cur, cur->begin()));
@@
-634,19
+636,19
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
DOUT << "no free registers\n";
// Compile the spill weights into an array that is better for scanning.
DOUT << "no free registers\n";
// Compile the spill weights into an array that is better for scanning.
- std::vector<float> SpillWeights(
m
ri_->getNumRegs(), 0.0);
+ std::vector<float> SpillWeights(
t
ri_->getNumRegs(), 0.0);
for (std::vector<std::pair<unsigned, float> >::iterator
I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
for (std::vector<std::pair<unsigned, float> >::iterator
I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
- updateSpillWeights(SpillWeights, I->first, I->second,
m
ri_);
+ updateSpillWeights(SpillWeights, I->first, I->second,
t
ri_);
// for each interval in active, update spill weights.
for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
i != e; ++i) {
unsigned reg = i->first->reg;
// for each interval in active, update spill weights.
for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
i != e; ++i) {
unsigned reg = i->first->reg;
- assert(
M
RegisterInfo::isVirtualRegister(reg) &&
+ assert(
Target
RegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
- updateSpillWeights(SpillWeights, reg, i->first->weight,
m
ri_);
+ updateSpillWeights(SpillWeights, reg, i->first->weight,
t
ri_);
}
DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
}
DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
@@
-672,7
+674,7
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
unsigned reg = *i;
// No need to worry about if the alias register size < regsize of RC.
// We are going to spill all registers that alias it anyway.
unsigned reg = *i;
// No need to worry about if the alias register size < regsize of RC.
// We are going to spill all registers that alias it anyway.
- for (const unsigned* as =
m
ri_->getAliasSet(reg); *as; ++as) {
+ for (const unsigned* as =
t
ri_->getAliasSet(reg); *as; ++as) {
if (minWeight > SpillWeights[*as]) {
minWeight = SpillWeights[*as];
minReg = *as;
if (minWeight > SpillWeights[*as]) {
minWeight = SpillWeights[*as];
minReg = *as;
@@
-686,7
+688,7
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
}
DOUT << "\t\tregister with min weight: "
}
DOUT << "\t\tregister with min weight: "
- <<
m
ri_->getName(minReg) << " (" << minWeight << ")\n";
+ <<
t
ri_->getName(minReg) << " (" << minWeight << ")\n";
// if the current has the minimum weight, we need to spill it and
// add any added intervals back to unhandled, and restart
// if the current has the minimum weight, we need to spill it and
// add any added intervals back to unhandled, and restart
@@
-717,13
+719,13
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
// minimum weight, rollback to the interval with the earliest
// start point and let the linear scan algorithm run again
std::vector<LiveInterval*> added;
// minimum weight, rollback to the interval with the earliest
// start point and let the linear scan algorithm run again
std::vector<LiveInterval*> added;
- assert(
M
RegisterInfo::isPhysicalRegister(minReg) &&
+ assert(
Target
RegisterInfo::isPhysicalRegister(minReg) &&
"did not choose a register to spill?");
"did not choose a register to spill?");
- BitVector toSpill(
m
ri_->getNumRegs());
+ BitVector toSpill(
t
ri_->getNumRegs());
// We are going to spill minReg and all its aliases.
toSpill[minReg] = true;
// We are going to spill minReg and all its aliases.
toSpill[minReg] = true;
- for (const unsigned* as =
m
ri_->getAliasSet(minReg); *as; ++as)
+ for (const unsigned* as =
t
ri_->getAliasSet(minReg); *as; ++as)
toSpill[*as] = true;
// the earliest start of a spilled interval indicates up to where
toSpill[*as] = true;
// the earliest start of a spilled interval indicates up to where
@@
-740,7
+742,7
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
// mark our rollback point.
for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
unsigned reg = i->first->reg;
// mark our rollback point.
for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
unsigned reg = i->first->reg;
- if (//
M
RegisterInfo::isVirtualRegister(reg) &&
+ if (//
Target
RegisterInfo::isVirtualRegister(reg) &&
toSpill[vrm_->getPhys(reg)] &&
cur->overlapsFrom(*i->first, i->second)) {
DOUT << "\t\t\tspilling(a): " << *i->first << '\n';
toSpill[vrm_->getPhys(reg)] &&
cur->overlapsFrom(*i->first, i->second)) {
DOUT << "\t\t\tspilling(a): " << *i->first << '\n';
@@
-753,7
+755,7
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
}
for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
unsigned reg = i->first->reg;
}
for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
unsigned reg = i->first->reg;
- if (//
M
RegisterInfo::isVirtualRegister(reg) &&
+ if (//
Target
RegisterInfo::isVirtualRegister(reg) &&
toSpill[vrm_->getPhys(reg)] &&
cur->overlapsFrom(*i->first, i->second-1)) {
DOUT << "\t\t\tspilling(i): " << *i->first << '\n';
toSpill[vrm_->getPhys(reg)] &&
cur->overlapsFrom(*i->first, i->second-1)) {
DOUT << "\t\t\tspilling(i): " << *i->first << '\n';
@@
-783,19
+785,19
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
IntervalPtrs::iterator it;
if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
active_.erase(it);
IntervalPtrs::iterator it;
if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
active_.erase(it);
- assert(!
M
RegisterInfo::isPhysicalRegister(i->reg));
+ assert(!
Target
RegisterInfo::isPhysicalRegister(i->reg));
if (!spilled.count(i->reg))
unhandled_.push(i);
prt_->delRegUse(vrm_->getPhys(i->reg));
vrm_->clearVirt(i->reg);
} else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
inactive_.erase(it);
if (!spilled.count(i->reg))
unhandled_.push(i);
prt_->delRegUse(vrm_->getPhys(i->reg));
vrm_->clearVirt(i->reg);
} else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
inactive_.erase(it);
- assert(!
M
RegisterInfo::isPhysicalRegister(i->reg));
+ assert(!
Target
RegisterInfo::isPhysicalRegister(i->reg));
if (!spilled.count(i->reg))
unhandled_.push(i);
vrm_->clearVirt(i->reg);
} else {
if (!spilled.count(i->reg))
unhandled_.push(i);
vrm_->clearVirt(i->reg);
} else {
- assert(
M
RegisterInfo::isVirtualRegister(i->reg) &&
+ assert(
Target
RegisterInfo::isVirtualRegister(i->reg) &&
"Can only allocate virtual registers!");
vrm_->clearVirt(i->reg);
unhandled_.push(i);
"Can only allocate virtual registers!");
vrm_->clearVirt(i->reg);
unhandled_.push(i);
@@
-822,7
+824,7
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
HI->expiredAt(cur->beginNumber())) {
DOUT << "\t\t\tundo changes for: " << *HI << '\n';
active_.push_back(std::make_pair(HI, HI->begin()));
HI->expiredAt(cur->beginNumber())) {
DOUT << "\t\t\tundo changes for: " << *HI << '\n';
active_.push_back(std::make_pair(HI, HI->begin()));
- assert(!
M
RegisterInfo::isPhysicalRegister(HI->reg));
+ assert(!
Target
RegisterInfo::isPhysicalRegister(HI->reg));
prt_->addRegUse(vrm_->getPhys(HI->reg));
}
}
prt_->addRegUse(vrm_->getPhys(HI->reg));
}
}
@@
-835,21
+837,21
@@
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
/// getFreePhysReg - return a free physical register for this virtual register
/// interval if we have one, otherwise return 0.
unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
/// getFreePhysReg - return a free physical register for this virtual register
/// interval if we have one, otherwise return 0.
unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
- std::vector<unsigned> inactiveCounts(
m
ri_->getNumRegs(), 0);
+ std::vector<unsigned> inactiveCounts(
t
ri_->getNumRegs(), 0);
unsigned MaxInactiveCount = 0;
unsigned MaxInactiveCount = 0;
- const TargetRegisterClass *RC = reg
map
_->getRegClass(cur->reg);
+ const TargetRegisterClass *RC = reg
info
_->getRegClass(cur->reg);
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
i != e; ++i) {
unsigned reg = i->first->reg;
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
i != e; ++i) {
unsigned reg = i->first->reg;
- assert(
M
RegisterInfo::isVirtualRegister(reg) &&
+ assert(
Target
RegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
// If this is not in a related reg class to the register we're allocating,
// don't check it.
"Can only allocate virtual registers!");
// If this is not in a related reg class to the register we're allocating,
// don't check it.
- const TargetRegisterClass *RegRC = reg
map
_->getRegClass(reg);
+ const TargetRegisterClass *RegRC = reg
info
_->getRegClass(reg);
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
reg = vrm_->getPhys(reg);
++inactiveCounts[reg];
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
reg = vrm_->getPhys(reg);
++inactiveCounts[reg];
@@
-865,11
+867,11
@@
unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
if (cur->preference)
if (prt_->isRegAvail(cur->preference)) {
DOUT << "\t\tassigned the preferred register: "
if (cur->preference)
if (prt_->isRegAvail(cur->preference)) {
DOUT << "\t\tassigned the preferred register: "
- <<
m
ri_->getName(cur->preference) << "\n";
+ <<
t
ri_->getName(cur->preference) << "\n";
return cur->preference;
} else
DOUT << "\t\tunable to assign the preferred register: "
return cur->preference;
} else
DOUT << "\t\tunable to assign the preferred register: "
- <<
m
ri_->getName(cur->preference) << "\n";
+ <<
t
ri_->getName(cur->preference) << "\n";
// Scan for the first available register.
TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
// Scan for the first available register.
TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);