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Fix some fixme's in #if 0'd code by making it dependent on the structural
[oota-llvm.git]
/
lib
/
CodeGen
/
RegAllocLocal.cpp
diff --git
a/lib/CodeGen/RegAllocLocal.cpp
b/lib/CodeGen/RegAllocLocal.cpp
index 311c0e7ffc90832fa267e865aca0747d8c14296f..e5d3a48babdf48e5cfef485225fb203d9e3590ad 100644
(file)
--- a/
lib/CodeGen/RegAllocLocal.cpp
+++ b/
lib/CodeGen/RegAllocLocal.cpp
@@
-25,6
+25,8
@@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallSet.h"
@@
-151,6
+153,7
@@
namespace {
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesCFG();
AU.addRequiredID(PHIEliminationID);
AU.addRequiredID(TwoAddressInstructionPassID);
MachineFunctionPass::getAnalysisUsage(AU);
AU.addRequiredID(PHIEliminationID);
AU.addRequiredID(TwoAddressInstructionPassID);
MachineFunctionPass::getAnalysisUsage(AU);
@@
-464,7
+467,7
@@
unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
}
}
-/// reloadVirtReg - This method transforms the specified
specified
virtual
+/// reloadVirtReg - This method transforms the specified virtual
/// register use to refer to a physical register. This method may do this in
/// one of several ways: if the register is available in a physical register
/// already, it uses that physical register. If the value is not in a physical
/// register use to refer to a physical register. This method may do this in
/// one of several ways: if the register is available in a physical register
/// already, it uses that physical register. If the value is not in a physical
@@
-517,24
+520,28
@@
MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
if (!ReloadedRegs.insert(PhysReg)) {
getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
if (!ReloadedRegs.insert(PhysReg)) {
- cerr << "Ran out of registers during register allocation!\n";
+ std::string msg;
+ raw_string_ostream Msg(msg);
+ Msg << "Ran out of registers during register allocation!";
if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
-
cerr << "
Please check your inline asm statement for invalid "
+
Msg << "\n
Please check your inline asm statement for invalid "
<< "constraints:\n";
<< "constraints:\n";
- MI->print(
cerr.stream()
, TM);
+ MI->print(
Msg
, TM);
}
}
-
exit(1
);
+
llvm_report_error(Msg.str()
);
}
for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
*SubRegs; ++SubRegs) {
if (!ReloadedRegs.insert(*SubRegs)) {
}
for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
*SubRegs; ++SubRegs) {
if (!ReloadedRegs.insert(*SubRegs)) {
- cerr << "Ran out of registers during register allocation!\n";
+ std::string msg;
+ raw_string_ostream Msg(msg);
+ Msg << "Ran out of registers during register allocation!";
if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
-
cerr << "
Please check your inline asm statement for invalid "
+
Msg << "\n
Please check your inline asm statement for invalid "
<< "constraints:\n";
<< "constraints:\n";
- MI->print(
cerr.stream()
, TM);
+ MI->print(
Msg
, TM);
}
}
-
exit(1
);
+
llvm_report_error(Msg.str()
);
}
}
}
}
@@
-708,7
+715,7
@@
void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
MachineBasicBlock::iterator MII = MBB.begin();
DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
MachineBasicBlock::iterator MII = MBB.begin();
DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
- if (LBB)
DOUT
<< "\nStarting RegAlloc of BB: " << LBB->getName());
+ if (LBB)
errs()
<< "\nStarting RegAlloc of BB: " << LBB->getName());
// Add live-in registers as active.
for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
// Add live-in registers as active.
for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
@@
-981,10
+988,12
@@
void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
}
}
}
- // Finally, if this is a noop copy instruction, zap it.
+ // Finally, if this is a noop copy instruction, zap it. (Except that if
+ // the copy is dead, it must be kept to avoid messing up liveness info for
+ // the register scavenger. See pr4100.)
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
- SrcReg == DstReg)
+ SrcReg == DstReg
&& DeadDefs.empty()
)
MBB.erase(MI);
}
MBB.erase(MI);
}