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Don't use a random type for the select condition,
[oota-llvm.git]
/
lib
/
CodeGen
/
RegAllocSimple.cpp
diff --git
a/lib/CodeGen/RegAllocSimple.cpp
b/lib/CodeGen/RegAllocSimple.cpp
index 87ef0031c586a85c24ddfbb4e63cc5cd9754b924..7dc98904abcc9b8625b41b8dd337ae91e4600a2b 100644
(file)
--- a/
lib/CodeGen/RegAllocSimple.cpp
+++ b/
lib/CodeGen/RegAllocSimple.cpp
@@
-2,8
+2,8
@@
//
// The LLVM Compiler Infrastructure
//
//
// The LLVM Compiler Infrastructure
//
-// This file
was developed by the LLVM research group and is distributed under
-//
the University of Illinois Open Source
License. See LICENSE.TXT for details.
+// This file
is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
//
@@
-18,8
+18,8
@@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
@@
-27,21
+27,26
@@
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
+#include <map>
using namespace llvm;
using namespace llvm;
-namespace {
- static Statistic NumStores("ra-simple", "Number of stores added");
- static Statistic NumLoads ("ra-simple", "Number of loads added");
+STATISTIC(NumStores, "Number of stores added");
+STATISTIC(NumLoads , "Number of loads added");
+namespace {
static RegisterRegAlloc
static RegisterRegAlloc
- simpleRegAlloc("simple", "
simple register allocator",
+ simpleRegAlloc("simple", "simple register allocator",
createSimpleRegisterAllocator);
class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
createSimpleRegisterAllocator);
class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
+ public:
+ static char ID;
+ RegAllocSimple() : MachineFunctionPass(&ID) {}
+ private:
MachineFunction *MF;
const TargetMachine *TM;
MachineFunction *MF;
const TargetMachine *TM;
- const
MRegisterInfo *RegInfo
;
-
bool *PhysRegsEverUsed
;
+ const
TargetRegisterInfo *TRI
;
+
const TargetInstrInfo *TII
;
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
@@
-91,7
+96,7
@@
namespace {
void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg);
};
void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg);
};
-
+ char RegAllocSimple::ID = 0;
}
/// getStackSpaceFor - This allocates space for the specified virtual
}
/// getStackSpaceFor - This allocates space for the specified virtual
@@
-99,10
+104,9
@@
namespace {
int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
const TargetRegisterClass *RC) {
// Find the location VirtReg would belong...
int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
const TargetRegisterClass *RC) {
// Find the location VirtReg would belong...
- std::map<unsigned, int>::iterator I =
- StackSlotForVirtReg.lower_bound(VirtReg);
+ std::map<unsigned, int>::iterator I = StackSlotForVirtReg.find(VirtReg);
- if (I != StackSlotForVirtReg.end()
&& I->first == VirtReg
)
+ if (I != StackSlotForVirtReg.end())
return I->second; // Already has space allocated?
// Allocate a new stack object for this spill location...
return I->second; // Already has space allocated?
// Allocate a new stack object for this spill location...
@@
-116,7
+120,7
@@
int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
}
unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
}
unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
- const TargetRegisterClass* RC = MF->get
SSARegMap()->
getRegClass(virtualReg);
+ const TargetRegisterClass* RC = MF->get
RegInfo().
getRegClass(virtualReg);
TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
@@
-126,7
+130,7
@@
unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
unsigned PhysReg = *(RI+regIdx);
if (!RegsUsed[PhysReg]) {
unsigned PhysReg = *(RI+regIdx);
if (!RegsUsed[PhysReg]) {
-
PhysRegsEverUsed[PhysReg] = true
;
+
MF->getRegInfo().setPhysRegUsed(PhysReg)
;
return PhysReg;
}
}
return PhysReg;
}
}
@@
-135,25
+139,26
@@
unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg) {
unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg) {
- const TargetRegisterClass* RC = MF->get
SSARegMap()->
getRegClass(VirtReg);
+ const TargetRegisterClass* RC = MF->get
RegInfo().
getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC);
unsigned PhysReg = getFreeReg(VirtReg);
// Add move instruction(s)
++NumLoads;
int FrameIdx = getStackSpaceFor(VirtReg, RC);
unsigned PhysReg = getFreeReg(VirtReg);
// Add move instruction(s)
++NumLoads;
-
RegInfo
->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+
TII
->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
return PhysReg;
}
void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
- const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
+ const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
+
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
++NumStores;
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
++NumStores;
-
RegInfo->storeRegToStackSlot(MBB, I, PhysReg
, FrameIdx, RC);
+
TII->storeRegToStackSlot(MBB, I, PhysReg, true
, FrameIdx, RC);
}
}
@@
-163,12
+168,11
@@
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- RegsUsed.resize(
RegInfo
->getNumRegs());
+ RegsUsed.resize(
TRI
->getNumRegs());
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
- unsigned Opcode = MI->getOpcode();
- const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
+ const TargetInstrDesc &Desc = MI->getDesc();
const unsigned *Regs;
if (Desc.ImplicitUses) {
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
const unsigned *Regs;
if (Desc.ImplicitUses) {
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
@@
-178,18
+182,18
@@
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (Desc.ImplicitDefs) {
for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
RegsUsed[*Regs] = true;
if (Desc.ImplicitDefs) {
for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
RegsUsed[*Regs] = true;
-
PhysRegsEverUsed[*Regs] = true
;
+
MF->getRegInfo().setPhysRegUsed(*Regs)
;
}
}
// Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
}
}
// Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand &
op
= MI->getOperand(i);
+ MachineOperand &
MO
= MI->getOperand(i);
- if (
op.isRegister() && op
.getReg() &&
-
MRegisterInfo::isVirtualRegister(op
.getReg())) {
- unsigned virtualReg = (unsigned)
op
.getReg();
- DOUT << "op: " <<
op
<< "\n";
+ if (
MO.isReg() && MO
.getReg() &&
+
TargetRegisterInfo::isVirtualRegister(MO
.getReg())) {
+ unsigned virtualReg = (unsigned)
MO
.getReg();
+ DOUT << "op: " <<
MO
<< "\n";
DOUT << "\t inst[" << i << "]: ";
DEBUG(MI->print(*cerr.stream(), TM));
DOUT << "\t inst[" << i << "]: ";
DEBUG(MI->print(*cerr.stream(), TM));
@@
-197,16
+201,15
@@
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
- if (op.isDef()) {
- int TiedOp = TM->getInstrInfo()
- ->findTiedToSrcOperand(MI->getOpcode(), i);
+ if (MO.isDef()) {
+ int TiedOp = Desc.findTiedToSrcOperand(i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {
// must be same register number as the source operand that is
// tied to. This maps a = b + c into b = b + c, and saves b into
// a's spot.
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {
// must be same register number as the source operand that is
// tied to. This maps a = b + c into b = b + c, and saves b into
// a's spot.
- assert(MI->getOperand(TiedOp).isReg
ister
() &&
+ assert(MI->getOperand(TiedOp).isReg() &&
MI->getOperand(TiedOp).getReg() &&
MI->getOperand(TiedOp).isUse() &&
"Two address instruction invalid!");
MI->getOperand(TiedOp).getReg() &&
MI->getOperand(TiedOp).isUse() &&
"Two address instruction invalid!");
@@
-219,8
+222,8
@@
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
Virt2PhysRegMap[virtualReg] = physReg;
}
}
Virt2PhysRegMap[virtualReg] = physReg;
}
}
- M
I->getOperand(i)
.setReg(physReg);
- DOUT << "virt: " << virtualReg << ", phys: " <<
op
.getReg() << "\n";
+ M
O
.setReg(physReg);
+ DOUT << "virt: " << virtualReg << ", phys: " <<
MO
.getReg() << "\n";
}
}
RegClassIdx.clear();
}
}
RegClassIdx.clear();
@@
-235,11
+238,8
@@
bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
DOUT << "Machine Function\n";
MF = &Fn;
TM = &MF->getTarget();
DOUT << "Machine Function\n";
MF = &Fn;
TM = &MF->getTarget();
- RegInfo = TM->getRegisterInfo();
-
- PhysRegsEverUsed = new bool[RegInfo->getNumRegs()];
- std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false);
- Fn.setUsedPhysRegs(PhysRegsEverUsed);
+ TRI = TM->getRegisterInfo();
+ TII = TM->getInstrInfo();
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();