-// This file was developed by the Evan Cheng and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
- RegInfo->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
+ TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(MBBI);
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(MBBI);
restoreScavengedReg();
// Process uses first.
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
restoreScavengedReg();
// Process uses first.
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
continue;
unsigned Reg = MO.getReg();
// If it's dead upon def, then it is now free.
continue;
unsigned Reg = MO.getReg();
// If it's dead upon def, then it is now free.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
const BitVector &Candidates) const {
// Mask off the registers which are not in the TargetRegisterClass.
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
const BitVector &Candidates) const {
// Mask off the registers which are not in the TargetRegisterClass.
- BitVector RegStatesCopy(NumPhysRegs, false);
- CreateRegClassMask(RegClass, RegStatesCopy);
- RegStatesCopy &= RegStates;
+ BitVector RegsAvailableCopy(NumPhysRegs, false);
+ CreateRegClassMask(RegClass, RegsAvailableCopy);
+ RegsAvailableCopy &= RegsAvailable;
return (Reg == -1) ? 0 : Reg;
}
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
bool ExCalleeSaved) const {
// Mask off the registers which are not in the TargetRegisterClass.
return (Reg == -1) ? 0 : Reg;
}
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
bool ExCalleeSaved) const {
// Mask off the registers which are not in the TargetRegisterClass.
- BitVector RegStatesCopy(NumPhysRegs, false);
- CreateRegClassMask(RegClass, RegStatesCopy);
- RegStatesCopy &= RegStates;
+ BitVector RegsAvailableCopy(NumPhysRegs, false);
+ CreateRegClassMask(RegClass, RegsAvailableCopy);
+ RegsAvailableCopy &= RegsAvailable;
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
- RegInfo->loadRegFromStackSlot(*MBB, I, ScavengedReg,
- ScavengingFrameIndex, ScavengedRC);
+ TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
+ ScavengingFrameIndex, ScavengedRC);
- RegInfo->storeRegToStackSlot(*MBB, I, SReg, ScavengingFrameIndex, RC);
+ TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);