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Don't use a random type for the select condition,
[oota-llvm.git]
/
lib
/
CodeGen
/
RegisterScavenging.cpp
diff --git
a/lib/CodeGen/RegisterScavenging.cpp
b/lib/CodeGen/RegisterScavenging.cpp
index c71d3be08b4123b73fa7236dcbf141bea02f8989..c1d7ff97e44e74711465e79c85441538b9e5d83e 100644
(file)
--- a/
lib/CodeGen/RegisterScavenging.cpp
+++ b/
lib/CodeGen/RegisterScavenging.cpp
@@
-35,13
+35,14
@@
static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
bool SeenSuperDef = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
bool SeenSuperDef = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg
ister
())
+ if (!MO.isReg())
continue;
continue;
- if (TRI->isSuperRegister(SubReg, MO.getReg()))
+ if (TRI->isSuperRegister(SubReg, MO.getReg()))
{
if (MO.isUse())
SeenSuperUse = true;
else if (MO.isImplicit())
SeenSuperDef = true;
if (MO.isUse())
SeenSuperUse = true;
else if (MO.isImplicit())
SeenSuperDef = true;
+ }
}
return SeenSuperDef && SeenSuperUse;
}
return SeenSuperDef && SeenSuperUse;
@@
-50,31
+51,37
@@
static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
static bool RedefinesSuperRegPart(const MachineInstr *MI,
const MachineOperand &MO,
const TargetRegisterInfo *TRI) {
static bool RedefinesSuperRegPart(const MachineInstr *MI,
const MachineOperand &MO,
const TargetRegisterInfo *TRI) {
- assert(MO.isReg
ister
() && MO.isDef() && "Not a register def!");
+ assert(MO.isReg() && MO.isDef() && "Not a register def!");
return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
}
/// setUsed - Set the register and its sub-registers as being used.
return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
}
/// setUsed - Set the register and its sub-registers as being used.
-void RegScavenger::setUsed(unsigned Reg) {
+void RegScavenger::setUsed(unsigned Reg
, bool ImpDef
) {
RegsAvailable.reset(Reg);
RegsAvailable.reset(Reg);
+ ImplicitDefed[Reg] = ImpDef;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs)
+ unsigned SubReg = *SubRegs; ++SubRegs)
{
RegsAvailable.reset(SubReg);
RegsAvailable.reset(SubReg);
+ ImplicitDefed[SubReg] = ImpDef;
+ }
}
/// setUnused - Set the register and its sub-registers as being unused.
void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
RegsAvailable.set(Reg);
}
/// setUnused - Set the register and its sub-registers as being unused.
void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
RegsAvailable.set(Reg);
+ ImplicitDefed.reset(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
- if (!RedefinesSuperRegPart(MI, Reg, TRI))
+ if (!RedefinesSuperRegPart(MI, Reg, TRI))
{
RegsAvailable.set(SubReg);
RegsAvailable.set(SubReg);
+ ImplicitDefed.reset(SubReg);
+ }
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
-
const
MachineFunction &MF = *mbb->getParent();
+ MachineFunction &MF = *mbb->getParent();
const TargetMachine &TM = MF.getTarget();
TII = TM.getInstrInfo();
TRI = TM.getRegisterInfo();
const TargetMachine &TM = MF.getTarget();
TII = TM.getInstrInfo();
TRI = TM.getRegisterInfo();
@@
-86,6
+93,7
@@
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
if (!MBB) {
NumPhysRegs = TRI->getNumRegs();
RegsAvailable.resize(NumPhysRegs);
if (!MBB) {
NumPhysRegs = TRI->getNumRegs();
RegsAvailable.resize(NumPhysRegs);
+ ImplicitDefed.resize(NumPhysRegs);
// Create reserved registers bitvector.
ReservedRegs = TRI->getReservedRegs(MF);
// Create reserved registers bitvector.
ReservedRegs = TRI->getReservedRegs(MF);
@@
-186,7
+194,7
@@
void RegScavenger::forward() {
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg
ister
() || !MO.isUse())
+ if (!MO.isReg() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
continue;
unsigned Reg = MO.getReg();
@@
-216,10
+224,11
@@
void RegScavenger::forward() {
setUnused(ChangedRegs);
// Process defs.
setUnused(ChangedRegs);
// Process defs.
+ bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg
ister
() || !MO.isDef())
+ if (!MO.isReg() || !MO.isDef())
continue;
unsigned Reg = MO.getReg();
continue;
unsigned Reg = MO.getReg();
@@
-240,12
+249,13
@@
void RegScavenger::forward() {
if (RedefinesSuperRegPart(MI, MO, TRI))
continue;
if (RedefinesSuperRegPart(MI, MO, TRI))
continue;
- // Implicit def is allowed to "re-define" any register.
+ // Implicit def is allowed to "re-define" any register. Similarly,
+ // implicitly defined registers can be clobbered.
assert((isReserved(Reg) || isUnused(Reg) ||
assert((isReserved(Reg) || isUnused(Reg) ||
-
MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF
||
+
IsImpDef || isImplicitlyDefined(Reg)
||
isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
"Re-defining a live register!");
isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
"Re-defining a live register!");
- setUsed(Reg);
+ setUsed(Reg
, IsImpDef
);
}
}
}
}
@@
-260,7
+270,7
@@
void RegScavenger::backward() {
const TargetInstrDesc &TID = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
const TargetInstrDesc &TID = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg
ister
() || !MO.isDef())
+ if (!MO.isReg() || !MO.isDef())
continue;
// Skip two-address destination operand.
if (TID.findTiedToSrcOperand(i) != -1)
continue;
// Skip two-address destination operand.
if (TID.findTiedToSrcOperand(i) != -1)
@@
-275,7
+285,7
@@
void RegScavenger::backward() {
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg
ister
() || !MO.isUse())
+ if (!MO.isReg() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
@@
-368,7
+378,7
@@
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
- if (MO.isReg
ister
())
+ if (MO.isReg())
Candidates.reset(MO.getReg());
}
Candidates.reset(MO.getReg());
}