projects
/
oota-llvm.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Teach machine cse to commute instructions.
[oota-llvm.git]
/
lib
/
CodeGen
/
ScheduleDAGEmit.cpp
diff --git
a/lib/CodeGen/ScheduleDAGEmit.cpp
b/lib/CodeGen/ScheduleDAGEmit.cpp
index ce3283dc3df1adda09f7c74886fa44db3c99217d..0a2fb3796a4239d65d766a8b094bff42b96238ce 100644
(file)
--- a/
lib/CodeGen/ScheduleDAGEmit.cpp
+++ b/
lib/CodeGen/ScheduleDAGEmit.cpp
@@
-28,44
+28,39
@@
#include "llvm/Support/MathExtras.h"
using namespace llvm;
#include "llvm/Support/MathExtras.h"
using namespace llvm;
-void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
- MI->addMemOperand(*MF, MO);
-}
-
void ScheduleDAG::EmitNoop() {
void ScheduleDAG::EmitNoop() {
- TII->insertNoop(*BB,
BB->end()
);
+ TII->insertNoop(*BB,
InsertPos
);
}
}
-void ScheduleDAG::Emit
CrossRC
Copy(SUnit *SU,
+void ScheduleDAG::Emit
PhysReg
Copy(SUnit *SU,
DenseMap<SUnit*, unsigned> &VRBaseMap) {
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
DenseMap<SUnit*, unsigned> &VRBaseMap) {
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
- if (I->isCtrl) continue; // ignore chain preds
- if (I->
Dep
->CopyDstRC) {
+ if (I->isCtrl
()
) continue; // ignore chain preds
+ if (I->
getSUnit()
->CopyDstRC) {
// Copy to physical register.
// Copy to physical register.
- DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->
Dep
);
+ DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->
getSUnit()
);
assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
// Find the destination physical register.
unsigned Reg = 0;
for (SUnit::const_succ_iterator II = SU->Succs.begin(),
EE = SU->Succs.end(); II != EE; ++II) {
assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
// Find the destination physical register.
unsigned Reg = 0;
for (SUnit::const_succ_iterator II = SU->Succs.begin(),
EE = SU->Succs.end(); II != EE; ++II) {
- if (I
->Reg
) {
- Reg = I
->Reg
;
+ if (I
I->getReg()
) {
+ Reg = I
I->getReg()
;
break;
}
}
break;
}
}
- assert(I->Reg && "Unknown physical register!");
- TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
- SU->CopyDstRC, SU->CopySrcRC);
+ BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
+ .addReg(VRI->second);
} else {
// Copy from physical register.
} else {
// Copy from physical register.
- assert(I->
Reg
&& "Unknown physical register!");
+ assert(I->
getReg()
&& "Unknown physical register!");
unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
- TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
-
SU->CopyDstRC, SU->CopySrcRC
);
+ BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
+
.addReg(I->getReg()
);
}
break;
}
}
break;
}