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Turn a 2-address instruction into a 3-address one when it's profitable even if the...
[oota-llvm.git]
/
lib
/
CodeGen
/
ScheduleDAGEmit.cpp
diff --git
a/lib/CodeGen/ScheduleDAGEmit.cpp
b/lib/CodeGen/ScheduleDAGEmit.cpp
index d10d670d346634a9ea5744516339541e5d77de23..770f5bbbdbb1d8d98a1bc4f4700a998ec9a96214 100644
(file)
--- a/
lib/CodeGen/ScheduleDAGEmit.cpp
+++ b/
lib/CodeGen/ScheduleDAGEmit.cpp
@@
-29,14
+29,14
@@
using namespace llvm;
void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
using namespace llvm;
void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
- MI->addMemOperand(
*
MF, MO);
+ MI->addMemOperand(MF, MO);
}
void ScheduleDAG::EmitNoop() {
}
void ScheduleDAG::EmitNoop() {
- TII->insertNoop(*BB,
BB->end()
);
+ TII->insertNoop(*BB,
InsertPos
);
}
}
-void ScheduleDAG::Emit
CrossRC
Copy(SUnit *SU,
+void ScheduleDAG::Emit
PhysReg
Copy(SUnit *SU,
DenseMap<SUnit*, unsigned> &VRBaseMap) {
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
DenseMap<SUnit*, unsigned> &VRBaseMap) {
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
@@
-49,13
+49,12
@@
void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
unsigned Reg = 0;
for (SUnit::const_succ_iterator II = SU->Succs.begin(),
EE = SU->Succs.end(); II != EE; ++II) {
unsigned Reg = 0;
for (SUnit::const_succ_iterator II = SU->Succs.begin(),
EE = SU->Succs.end(); II != EE; ++II) {
- if (I->getReg()) {
- Reg = I->getReg();
+ if (I
I
->getReg()) {
+ Reg = I
I
->getReg();
break;
}
}
break;
}
}
- assert(I->getReg() && "Unknown physical register!");
- TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
+ TII->copyRegToReg(*BB, InsertPos, Reg, VRI->second,
SU->CopyDstRC, SU->CopySrcRC);
} else {
// Copy from physical register.
SU->CopyDstRC, SU->CopySrcRC);
} else {
// Copy from physical register.
@@
-64,7
+63,7
@@
void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
- TII->copyRegToReg(*BB,
BB->end()
, VRBase, I->getReg(),
+ TII->copyRegToReg(*BB,
InsertPos
, VRBase, I->getReg(),
SU->CopyDstRC, SU->CopySrcRC);
}
break;
SU->CopyDstRC, SU->CopySrcRC);
}
break;