-SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
- SDOperand InL, InH;
- GetExpandedInteger(N->getOperand(0), InL, InH);
- // Just truncate the low part of the source.
- return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
-}
-
-SDOperand DAGTypeLegalizer::ExpandIntOp_BIT_CONVERT(SDNode *N) {
- if (N->getValueType(0).isVector()) {
- // An illegal integer type is being converted to a legal vector type.
- // Make a two element vector out of the expanded parts and convert that
- // instead, but only if the new vector type is legal (otherwise there
- // is no point, and it might create expansion loops). For example, on
- // x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32.
- MVT OVT = N->getOperand(0).getValueType();
- MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
-
- if (isTypeLegal(NVT)) {
- SDOperand Parts[2];
- GetExpandedInteger(N->getOperand(0), Parts[0], Parts[1]);
-
- if (TLI.isBigEndian())
- std::swap(Parts[0], Parts[1]);
-
- SDOperand Vec = DAG.getNode(ISD::BUILD_VECTOR, NVT, Parts, 2);
- return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Vec);
- }
- }
-
- // Otherwise, store to a temporary and load out again as the new type.
- return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
-}
-
-SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source,
- MVT DestTy) {
- // We know the destination is legal, but that the input needs to be expanded.
- MVT SourceVT = Source.getValueType();
-
- // Check to see if the target has a custom way to lower this. If so, use it.
- switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
- default: assert(0 && "This action not implemented for this operation!");
- case TargetLowering::Legal:
- case TargetLowering::Expand:
- break; // This case is handled below.
- case TargetLowering::Custom:
- SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
- Source), DAG);
- if (NV.Val) return NV;
- break; // The target lowered this.
- }
-
- RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (SourceVT == MVT::i64) {
- if (DestTy == MVT::f32)
- LC = RTLIB::SINTTOFP_I64_F32;
- else {
- assert(DestTy == MVT::f64 && "Unknown fp value type!");
- LC = RTLIB::SINTTOFP_I64_F64;
- }
- } else if (SourceVT == MVT::i128) {
- if (DestTy == MVT::f32)
- LC = RTLIB::SINTTOFP_I128_F32;
- else if (DestTy == MVT::f64)
- LC = RTLIB::SINTTOFP_I128_F64;
- else if (DestTy == MVT::f80)
- LC = RTLIB::SINTTOFP_I128_F80;
- else {
- assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
- LC = RTLIB::SINTTOFP_I128_PPCF128;
- }
- } else {
- assert(0 && "Unknown int value type!");
- }
-
- assert(LC != RTLIB::UNKNOWN_LIBCALL &&
- "Don't know how to expand this SINT_TO_FP!");
- return MakeLibCall(LC, DestTy, &Source, 1, true);
-}
-
-SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDOperand Source,
- MVT DestTy) {
- // We know the destination is legal, but that the input needs to be expanded.
- assert(getTypeAction(Source.getValueType()) == ExpandInteger &&
- "This is not an expansion!");
-
- // If this is unsigned, and not supported, first perform the conversion to
- // signed, then adjust the result if the sign bit is set.
- SDOperand SignedConv = ExpandIntOp_SINT_TO_FP(Source, DestTy);
-
- // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
- // incoming integer is set. To handle this, we dynamically test to see if
- // it is set, and, if so, add a fudge factor.
- SDOperand Lo, Hi;
- GetExpandedInteger(Source, Lo, Hi);
-
- SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
- DAG.getConstant(0, Hi.getValueType()),
- ISD::SETLT);
- SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
- SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
- SignSet, Four, Zero);
- uint64_t FF = 0x5f800000ULL;
- if (TLI.isLittleEndian()) FF <<= 32;
- Constant *FudgeFactor = ConstantInt::get((Type*)Type::Int64Ty, FF);
-
- SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
- CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
- SDOperand FudgeInReg;
- if (DestTy == MVT::f32)
- FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
- else if (DestTy.bitsGT(MVT::f32))
- // FIXME: Avoid the extend by construction the right constantpool?
- FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
- CPIdx, NULL, 0, MVT::f32);
- else
- assert(0 && "Unexpected conversion");
-
- return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
-}
-
-SDOperand DAGTypeLegalizer::ExpandIntOp_EXTRACT_ELEMENT(SDNode *N) {
- SDOperand Lo, Hi;
- GetExpandedInteger(N->getOperand(0), Lo, Hi);
- return cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
-}
-
-SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
- ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
- ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
-
- // If ExpandSetCCOperands returned a scalar, we need to compare the result
- // against zero to select between true and false values.
- if (NewRHS.Val == 0) {
- NewRHS = DAG.getConstant(0, NewLHS.getValueType());
- CCCode = ISD::SETNE;
- }
-
- // Update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
- DAG.getCondCode(CCCode), NewLHS, NewRHS,
- N->getOperand(4));
-}
-
-SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
- SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
- ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
- ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
-
- // If ExpandSetCCOperands returned a scalar, use it.
- if (NewRHS.Val == 0) return NewLHS;
-
- // Otherwise, update N to have the operands specified.
- return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
- DAG.getCondCode(CCCode));
-}
-
-/// ExpandSetCCOperands - Expand the operands of a comparison. This code is
-/// shared among BR_CC, SELECT_CC, and SETCC handlers.
-void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
- ISD::CondCode &CCCode) {
- SDOperand LHSLo, LHSHi, RHSLo, RHSHi;