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SelectionDAG switch lowering: Replace unreachable default with most popular case.
[oota-llvm.git]
/
lib
/
CodeGen
/
SelectionDAG
/
TargetLowering.cpp
diff --git
a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index db03e2ad8fdcbc5c169130a7e782fc515a3395d3..9aef5edcd54f60ad7f3abec158b37878751aad8f 100644
(file)
--- a/
lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/
lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@
-35,10
+35,9
@@
#include <cctype>
using namespace llvm;
#include <cctype>
using namespace llvm;
-/// NOTE: The constructor takes ownership of TLOF.
-TargetLowering::TargetLowering(const TargetMachine &tm,
- const TargetLoweringObjectFile *tlof)
- : TargetLoweringBase(tm, tlof) {}
+/// NOTE: The TargetMachine owns TLOF.
+TargetLowering::TargetLowering(const TargetMachine &tm)
+ : TargetLoweringBase(tm) {}
const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
return nullptr;
const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
return nullptr;
@@
-2703,7
+2702,7
@@
SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
SelectionDAG &DAG, bool IsAfterLegalization,
std::vector<SDNode *> *Created) const {
assert(Created && "No vector to hold udiv ops.");
SelectionDAG &DAG, bool IsAfterLegalization,
std::vector<SDNode *> *Created) const {
assert(Created && "No vector to hold udiv ops.");
-
+
EVT VT = N->getValueType(0);
SDLoc dl(N);
EVT VT = N->getValueType(0);
SDLoc dl(N);
@@
-2780,7
+2779,7
@@
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
SelectionDAG &DAG, SDValue LL, SDValue LH,
bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
SelectionDAG &DAG, SDValue LL, SDValue LH,
- SDValue RL, SDValue RH) const {
+
SDValue RL, SDValue RH) const {
EVT VT = N->getValueType(0);
SDLoc dl(N);
EVT VT = N->getValueType(0);
SDLoc dl(N);
@@
-2813,8
+2812,8
@@
bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
// The inputs are both zero-extended.
if (HasUMUL_LOHI) {
// We can emit a umul_lohi.
// The inputs are both zero-extended.
if (HasUMUL_LOHI) {
// We can emit a umul_lohi.
- Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
-
DAG.getVTList(HiLoVT, HiLoVT), LL,
RL);
+ Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
DAG.getVTList(HiLoVT, HiLoVT), LL,
+ RL);
Hi = SDValue(Lo.getNode(), 1);
return true;
}
Hi = SDValue(Lo.getNode(), 1);
return true;
}
@@
-2829,8
+2828,8
@@
bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
// The input values are both sign-extended.
if (HasSMUL_LOHI) {
// We can emit a smul_lohi.
// The input values are both sign-extended.
if (HasSMUL_LOHI) {
// We can emit a smul_lohi.
- Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
-
DAG.getVTList(HiLoVT, HiLoVT), LL,
RL);
+ Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
DAG.getVTList(HiLoVT, HiLoVT), LL,
+ RL);
Hi = SDValue(Lo.getNode(), 1);
return true;
}
Hi = SDValue(Lo.getNode(), 1);
return true;
}