- SplitAnalysis &sa_;
- LiveIntervals &lis_;
- VirtRegMap &vrm_;
- MachineRegisterInfo &mri_;
- const TargetInstrInfo &tii_;
-
- /// edit_ - The current parent register and new intervals created.
- LiveRangeEdit &edit_;
-
- /// dupli_ - Created as a copy of curli_, ranges are carved out as new
- /// intervals get added through openIntv / closeIntv. This is used to avoid
- /// editing curli_.
- LiveIntervalMap dupli_;
-
- /// Currently open LiveInterval.
- LiveIntervalMap openli_;
-
- /// intervalsLiveAt - Return true if any member of intervals_ is live at Idx.
- bool intervalsLiveAt(SlotIndex Idx) const;
-
- /// Values in curli whose live range has been truncated when entering an open
- /// li.
- SmallPtrSet<const VNInfo*, 8> truncatedValues;
-
- /// addTruncSimpleRange - Add the given simple range to dupli_ after
- /// truncating any overlap with intervals_.
- void addTruncSimpleRange(SlotIndex Start, SlotIndex End, VNInfo *VNI);
-
- /// criticalPreds_ - Set of basic blocks where both dupli and openli should be
- /// live out because of a critical edge.
- SplitAnalysis::BlockPtrSet criticalPreds_;
-
- /// computeRemainder - Compute the dupli liveness as the complement of all the
- /// new intervals.
- void computeRemainder();
-
- /// rewrite - Rewrite all uses of reg to use the new registers.
- void rewrite(unsigned reg);
+ SplitAnalysis &SA;
+ LiveIntervals &LIS;
+ VirtRegMap &VRM;
+ MachineRegisterInfo &MRI;
+ MachineDominatorTree &MDT;
+ const TargetInstrInfo &TII;
+ const TargetRegisterInfo &TRI;
+
+ /// Edit - The current parent register and new intervals created.
+ LiveRangeEdit &Edit;
+
+ /// Index into Edit of the currently open interval.
+ /// The index 0 is used for the complement, so the first interval started by
+ /// openIntv will be 1.
+ unsigned OpenIdx;
+
+ typedef IntervalMap<SlotIndex, unsigned> RegAssignMap;
+
+ /// Allocator for the interval map. This will eventually be shared with
+ /// SlotIndexes and LiveIntervals.
+ RegAssignMap::Allocator Allocator;
+
+ /// RegAssign - Map of the assigned register indexes.
+ /// Edit.get(RegAssign.lookup(Idx)) is the register that should be live at
+ /// Idx.
+ RegAssignMap RegAssign;
+
+ /// LIMappers - One LiveIntervalMap or each interval in Edit.
+ SmallVector<LiveIntervalMap, 4> LIMappers;
+
+ /// defFromParent - Define Reg from ParentVNI at UseIdx using either
+ /// rematerialization or a COPY from parent. Return the new value.
+ VNInfo *defFromParent(unsigned RegIdx,
+ VNInfo *ParentVNI,
+ SlotIndex UseIdx,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I);
+
+ /// rewriteAssigned - Rewrite all uses of Edit.getReg() to assigned registers.
+ void rewriteAssigned();
+
+ /// rewriteComponents - Rewrite all uses of Intv[0] according to the eq
+ /// classes in ConEQ.
+ /// This must be done when Intvs[0] is styill live at all uses, before calling
+ /// ConEq.Distribute().
+ void rewriteComponents(const SmallVectorImpl<LiveInterval*> &Intvs,
+ const ConnectedVNInfoEqClasses &ConEq);