-/// eliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
-/// of the de-ssa process. This replaces sources of REG_SEQUENCE as
-/// sub-register references of the register defined by REG_SEQUENCE. e.g.
-///
-/// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
-/// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
-/// =>
-/// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
-bool TwoAddressInstructionPass::eliminateRegSequences() {
- if (RegSequences.empty())
- return false;
-
- for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
- MachineInstr *MI = RegSequences[i];
- unsigned DstReg = MI->getOperand(0).getReg();
- if (MI->getOperand(0).getSubReg() ||
- TargetRegisterInfo::isPhysicalRegister(DstReg) ||
- !(MI->getNumOperands() & 1)) {
- DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
- llvm_unreachable(0);
- }
-
- bool IsImpDef = true;
- SmallVector<unsigned, 4> RealSrcs;
- SmallSet<unsigned, 4> Seen;
- for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
- // Nothing needs to be inserted for <undef> operands.
- if (MI->getOperand(i).isUndef()) {
- MI->getOperand(i).setReg(0);
- continue;
- }
- unsigned SrcReg = MI->getOperand(i).getReg();
- unsigned SrcSubIdx = MI->getOperand(i).getSubReg();
- unsigned SubIdx = MI->getOperand(i+1).getImm();
- // DefMI of NULL means the value does not have a vreg in this block
- // i.e., its a physical register or a subreg.
- // In either case we force a copy to be generated.
- MachineInstr *DefMI = NULL;
- if (!MI->getOperand(i).getSubReg() &&
- !TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
- DefMI = MRI->getUniqueVRegDef(SrcReg);
- }
+ bool DefEmitted = false;
+ for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
+ MachineOperand &UseMO = MI->getOperand(i);
+ unsigned SrcReg = UseMO.getReg();
+ unsigned SubIdx = MI->getOperand(i+1).getImm();
+ // Nothing needs to be inserted for <undef> operands.
+ if (UseMO.isUndef())
+ continue;