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Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backends
[oota-llvm.git]
/
lib
/
CodeGen
/
VirtRegMap.cpp
diff --git
a/lib/CodeGen/VirtRegMap.cpp
b/lib/CodeGen/VirtRegMap.cpp
index f87c8b06d15ead0e35651409ee39aa53714d384f..7b41e21d7017ad739f0c4893d80e4a1e8debaf47 100644
(file)
--- a/
lib/CodeGen/VirtRegMap.cpp
+++ b/
lib/CodeGen/VirtRegMap.cpp
@@
-16,7
+16,6
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "regalloc"
#include "llvm/CodeGen/VirtRegMap.h"
#include "LiveDebugVariables.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "LiveDebugVariables.h"
#include "llvm/ADT/STLExtras.h"
@@
-37,9
+36,12
@@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
using namespace llvm;
#include <algorithm>
using namespace llvm;
+#define DEBUG_TYPE "regalloc"
+
STATISTIC(NumSpillSlots, "Number of spill slots allocated");
STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
STATISTIC(NumSpillSlots, "Number of spill slots allocated");
STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
@@
-53,8
+55,8
@@
INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
MRI = &mf.getRegInfo();
bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
MRI = &mf.getRegInfo();
- TII = mf.get
T
arget().getInstrInfo();
- TRI = mf.get
T
arget().getRegisterInfo();
+ TII = mf.get
Subt
arget().getInstrInfo();
+ TRI = mf.get
Subt
arget().getRegisterInfo();
MF = &mf;
Virt2PhysMap.clear();
MF = &mf;
Virt2PhysMap.clear();
@@
-204,8
+206,8
@@
void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
MF = &fn;
TM = &MF->getTarget();
bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
MF = &fn;
TM = &MF->getTarget();
- TRI = TM->getRegisterInfo();
- TII = TM->getInstrInfo();
+ TRI = TM->get
SubtargetImpl()->get
RegisterInfo();
+ TII = TM->get
SubtargetImpl()->get
InstrInfo();
MRI = &MF->getRegInfo();
Indexes = &getAnalysis<SlotIndexes>();
LIS = &getAnalysis<LiveIntervals>();
MRI = &MF->getRegInfo();
Indexes = &getAnalysis<SlotIndexes>();
LIS = &getAnalysis<LiveIntervals>();
@@
-418,10
+420,8
@@
void VirtRegRewriter::rewrite() {
// Check if this register has a use that will impact the rest of the
// code. Uses in debug and noreturn instructions do not impact the
// generated code.
// Check if this register has a use that will impact the rest of the
// code. Uses in debug and noreturn instructions do not impact the
// generated code.
- for (MachineRegisterInfo::reg_nodbg_iterator It =
- MRI->reg_nodbg_begin(Reg),
- EndIt = MRI->reg_nodbg_end(); It != EndIt; ++It) {
- if (!NoReturnInsts.count(&(*It))) {
+ for (MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) {
+ if (!NoReturnInsts.count(&It)) {
MRI->setPhysRegUsed(Reg);
break;
}
MRI->setPhysRegUsed(Reg);
break;
}