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Remove the need to cache the subtarget in the ARM TargetRegisterInfo
[oota-llvm.git]
/
lib
/
Target
/
AArch64
/
AArch64ISelLowering.h
diff --git
a/lib/Target/AArch64/AArch64ISelLowering.h
b/lib/Target/AArch64/AArch64ISelLowering.h
index 4ad859184402a7adaa99936e1eda57b9d39e7742..b3b9986a319681d70689d5ae15fc0bfaafafdcad 100644
(file)
--- a/
lib/Target/AArch64/AArch64ISelLowering.h
+++ b/
lib/Target/AArch64/AArch64ISelLowering.h
@@
-141,6
+141,18
@@
enum {
FCMLEz,
FCMLTz,
FCMLEz,
FCMLTz,
+ // Vector across-lanes addition
+ // Only the lower result lane is defined.
+ SADDV,
+ UADDV,
+
+ // Vector across-lanes min/max
+ // Only the lower result lane is defined.
+ SMINV,
+ UMINV,
+ SMAXV,
+ UMAXV,
+
// Vector bitwise negation
NOT,
// Vector bitwise negation
NOT,
@@
-335,7
+347,8
@@
public:
bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
- bool shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
+ TargetLoweringBase::AtomicRMWExpansionKind
+ shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
bool useLoadStackGuardNode() const override;
TargetLoweringBase::LegalizeTypeAction
bool useLoadStackGuardNode() const override;
TargetLoweringBase::LegalizeTypeAction