-MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
- unsigned OpNum, int FI) const {
- unsigned Opc = MI->getOpcode();
- MachineInstr *NewMI = NULL;
- switch (Opc) {
- default: break;
- case ARM::MOVr: {
- if (OpNum == 0) { // move -> store
- unsigned SrcReg = MI->getOperand(1).getReg();
- NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
- .addReg(0).addImm(0);
- } else { // move -> load
- unsigned DstReg = MI->getOperand(0).getReg();
- NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
- .addImm(0);
- }
- break;
- }
- case ARM::tMOVr: {
- if (OpNum == 0) { // move -> store
- unsigned SrcReg = MI->getOperand(1).getReg();
- if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
- // tSpill cannot take a high register operand.
- break;
- NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
- .addImm(0);
- } else { // move -> load
- unsigned DstReg = MI->getOperand(0).getReg();
- if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
- // tRestore cannot target a high register operand.
- break;
- NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
- .addImm(0);
- }
- break;
- }
- case ARM::FCPYS: {
- if (OpNum == 0) { // move -> store
- unsigned SrcReg = MI->getOperand(1).getReg();
- NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
- .addImm(0);
- } else { // move -> load
- unsigned DstReg = MI->getOperand(0).getReg();
- NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0);
- }
- break;
- }
- case ARM::FCPYD: {
- if (OpNum == 0) { // move -> store
- unsigned SrcReg = MI->getOperand(1).getReg();
- NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
- .addImm(0);
- } else { // move -> load
- unsigned DstReg = MI->getOperand(0).getReg();
- NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0);
+const TargetRegisterClass*
+ARMRegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
+ if (STI.isThumb()) {
+ if (isLowRegister(Reg))
+ return ARM::tGPRRegisterClass;
+ switch (Reg) {
+ default:
+ break;
+ case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
+ case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
+ return ARM::GPRRegisterClass;