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Add comment.
[oota-llvm.git]
/
lib
/
Target
/
ARM
/
ARMRegisterInfo.td
diff --git
a/lib/Target/ARM/ARMRegisterInfo.td
b/lib/Target/ARM/ARMRegisterInfo.td
index 400c8c2649715e05cffd2da828efd60d8c7d8141..61c77e64acf78144e5172a1738a52b06b1d8e71d 100644
(file)
--- a/
lib/Target/ARM/ARMRegisterInfo.td
+++ b/
lib/Target/ARM/ARMRegisterInfo.td
@@
-2,8
+2,7
@@
//
// The LLVM Compiler Infrastructure
//
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the "Instituto Nokia de Tecnologia" and
-// is distributed under the University of Illinois Open Source
+// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
@@
-158,7
+157,7
@@
def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
GPRClass::iterator
GPRClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
GPRClass::iterator
GPRClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const
M
RegisterInfo *RI = TM.getRegisterInfo();
+ const
Target
RegisterInfo *RI = TM.getRegisterInfo();
const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
GPRClass::iterator I;
if (Subtarget.isThumb())
const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
GPRClass::iterator I;
if (Subtarget.isThumb())