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Cache the TargetLowering info object as a pointer.
[oota-llvm.git]
/
lib
/
Target
/
ARM
/
ARMScheduleV6.td
diff --git
a/lib/Target/ARM/ARMScheduleV6.td
b/lib/Target/ARM/ARMScheduleV6.td
index c1880a72fff39b9522614bf44419e75bcb989e43..0ace9bc1796d02ac3ad10147d53b33f8533c2d24 100644
(file)
--- a/
lib/Target/ARM/ARMScheduleV6.td
+++ b/
lib/Target/ARM/ARMScheduleV6.td
@@
-1,10
+1,10
@@
-//===-
ARMScheduleV6.td - ARM v6 Scheduling Definitions -
---*- tablegen -*-===//
-//
+//===-
- ARMScheduleV6.td - ARM v6 Scheduling Definitions
---*- tablegen -*-===//
+//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the ARM v6 processors.
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the ARM v6 processors.
@@
-243,6
+243,12
@@
def ARMV6Itineraries : ProcessorItineraries<
// Double-precision FP MAC
InstrItinData<IIC_fpMAC64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>,
//
// Double-precision FP MAC
InstrItinData<IIC_fpMAC64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>,
//
+ // Single-precision Fused FP MAC
+ InstrItinData<IIC_fpFMAC32, [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>,
+ //
+ // Double-precision Fused FP MAC
+ InstrItinData<IIC_fpFMAC64, [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>,
+ //
// Single-precision FP DIV
InstrItinData<IIC_fpDIV32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>,
//
// Single-precision FP DIV
InstrItinData<IIC_fpDIV32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>,
//