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[WinEH] Fix xdata generation when no catch object is present
[oota-llvm.git]
/
lib
/
Target
/
ARM
/
ARMTargetMachine.h
diff --git
a/lib/Target/ARM/ARMTargetMachine.h
b/lib/Target/ARM/ARMTargetMachine.h
index 8b559682211dada5ebf6dd79c174395cf8c3437b..20ca97b616b7f39d057a26ef6bf1fee871e100fb 100644
(file)
--- a/
lib/Target/ARM/ARMTargetMachine.h
+++ b/
lib/Target/ARM/ARMTargetMachine.h
@@
-11,8
+11,8
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#ifndef ARMTARGETMACHINE_H
-#define ARMTARGETMACHINE_H
+#ifndef
LLVM_LIB_TARGET_ARM_
ARMTARGETMACHINE_H
+#define
LLVM_LIB_TARGET_ARM_
ARMTARGETMACHINE_H
#include "ARMInstrInfo.h"
#include "ARMSubtarget.h"
#include "ARMInstrInfo.h"
#include "ARMSubtarget.h"
@@
-22,8
+22,19
@@
namespace llvm {
class ARMBaseTargetMachine : public LLVMTargetMachine {
namespace llvm {
class ARMBaseTargetMachine : public LLVMTargetMachine {
+public:
+ enum ARMABI {
+ ARM_ABI_UNKNOWN,
+ ARM_ABI_APCS,
+ ARM_ABI_AAPCS // ARM EABI
+ } TargetABI;
+
protected:
protected:
+ std::unique_ptr<TargetLoweringObjectFile> TLOF;
ARMSubtarget Subtarget;
ARMSubtarget Subtarget;
+ bool isLittle;
+ mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
+
public:
ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
public:
ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
@@
-31,16
+42,21
@@
public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool isLittle);
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool isLittle);
+ ~ARMBaseTargetMachine() override;
- const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
+ const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
+ const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
+ bool isLittleEndian() const { return isLittle; }
- /// \brief
Register ARM analysis passes with a pass manager
.
-
void addAnalysisPasses(PassManagerBase &PM
) override;
+ /// \brief
Get the TargetIRAnalysis for this target
.
+
TargetIRAnalysis getTargetIRAnalysis(
) override;
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
- bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
+ TargetLoweringObjectFile *getObjFileLowering() const override {
+ return TLOF.get();
+ }
};
/// ARMTargetMachine - ARM target machine.
};
/// ARMTargetMachine - ARM target machine.