- static ARMOperand CreateToken(StringRef Str) {
- ARMOperand Res;
- Res.Kind = Token;
- Res.Tok.Data = Str.data();
- Res.Tok.Length = Str.size();
- return Res;
- }
-
- static ARMOperand CreateReg(unsigned RegNum, bool Writeback) {
- ARMOperand Res;
- Res.Kind = Register;
- Res.Reg.RegNum = RegNum;
- Res.Reg.Writeback = Writeback;
- return Res;
- }
-
- static ARMOperand CreateImm(const MCExpr *Val) {
- ARMOperand Res;
- Res.Kind = Immediate;
- Res.Imm.Val = Val;
- return Res;
- }
-
- static ARMOperand CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
- const MCExpr *Offset, unsigned OffsetRegNum,
- bool OffsetRegShifted, enum ShiftType ShiftType,
- const MCExpr *ShiftAmount, bool Preindexed,
- bool Postindexed, bool Negative, bool Writeback) {
- ARMOperand Res;
- Res.Kind = Memory;
- Res.Mem.BaseRegNum = BaseRegNum;
- Res.Mem.OffsetIsReg = OffsetIsReg;
- Res.Mem.Offset = Offset;
- Res.Mem.OffsetRegNum = OffsetRegNum;
- Res.Mem.OffsetRegShifted = OffsetRegShifted;
- Res.Mem.ShiftType = ShiftType;
- Res.Mem.ShiftAmount = ShiftAmount;
- Res.Mem.Preindexed = Preindexed;
- Res.Mem.Postindexed = Postindexed;
- Res.Mem.Negative = Negative;
- Res.Mem.Writeback = Writeback;
- return Res;
+ void addRegListOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ const SmallVectorImpl<unsigned> &RegList = getRegList();
+ for (SmallVectorImpl<unsigned>::const_iterator
+ I = RegList.begin(), E = RegList.end(); I != E; ++I)
+ Inst.addOperand(MCOperand::CreateReg(*I));
+ }
+
+ void addImmOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ addExpr(Inst, getImm());
+ }
+
+ void addMemMode5Operands(MCInst &Inst, unsigned N) const {
+ assert(N == 2 && isMemMode5() && "Invalid number of operands!");
+
+ Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+ assert(!Mem.OffsetIsReg && "Invalid mode 5 operand");
+
+ // FIXME: #-0 is encoded differently than #0. Does the parser preserve
+ // the difference?
+ if (Mem.Offset) {
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
+ assert(CE && "Non-constant mode 5 offset operand!");
+
+ // The MCInst offset operand doesn't include the low two bits (like
+ // the instruction encoding).
+ int64_t Offset = CE->getValue() / 4;
+ if (Offset >= 0)
+ Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
+ Offset)));
+ else
+ Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
+ -Offset)));
+ } else {
+ Inst.addOperand(MCOperand::CreateImm(0));
+ }
+ }
+
+ virtual void dump(raw_ostream &OS) const;
+
+ static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
+ ARMOperand *Op = new ARMOperand(CondCode);
+ Op->CC.Val = CC;
+ Op->StartLoc = S;
+ Op->EndLoc = S;
+ return Op;
+ }
+
+ static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
+ ARMOperand *Op = new ARMOperand(Token);
+ Op->Tok.Data = Str.data();
+ Op->Tok.Length = Str.size();
+ Op->StartLoc = S;
+ Op->EndLoc = S;
+ return Op;
+ }
+
+ static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
+ SMLoc E) {
+ ARMOperand *Op = new ARMOperand(Register);
+ Op->Reg.RegNum = RegNum;
+ Op->Reg.Writeback = Writeback;
+ Op->StartLoc = S;
+ Op->EndLoc = E;
+ return Op;
+ }
+
+ static ARMOperand *
+ CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
+ SMLoc S, SMLoc E) {
+ ARMOperand *Op = new ARMOperand(RegisterList);
+ Op->RegList.Registers = new SmallVector<unsigned, 32>();
+ for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
+ I = Regs.begin(), E = Regs.end(); I != E; ++I)
+ Op->RegList.Registers->push_back(I->first);
+ std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end());
+ Op->StartLoc = S;
+ Op->EndLoc = E;
+ return Op;
+ }
+
+ static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
+ ARMOperand *Op = new ARMOperand(Immediate);
+ Op->Imm.Val = Val;
+ Op->StartLoc = S;
+ Op->EndLoc = E;
+ return Op;
+ }
+
+ static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
+ const MCExpr *Offset, unsigned OffsetRegNum,
+ bool OffsetRegShifted, enum ShiftType ShiftType,
+ const MCExpr *ShiftAmount, bool Preindexed,
+ bool Postindexed, bool Negative, bool Writeback,
+ SMLoc S, SMLoc E) {
+ ARMOperand *Op = new ARMOperand(Memory);
+ Op->Mem.BaseRegNum = BaseRegNum;
+ Op->Mem.OffsetIsReg = OffsetIsReg;
+ Op->Mem.Offset = Offset;
+ Op->Mem.OffsetRegNum = OffsetRegNum;
+ Op->Mem.OffsetRegShifted = OffsetRegShifted;
+ Op->Mem.ShiftType = ShiftType;
+ Op->Mem.ShiftAmount = ShiftAmount;
+ Op->Mem.Preindexed = Preindexed;
+ Op->Mem.Postindexed = Postindexed;
+ Op->Mem.Negative = Negative;
+ Op->Mem.Writeback = Writeback;
+
+ Op->StartLoc = S;
+ Op->EndLoc = E;
+ return Op;