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[Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
[oota-llvm.git]
/
lib
/
Target
/
ARM64
/
ARM64TargetTransformInfo.cpp
diff --git
a/lib/Target/ARM64/ARM64TargetTransformInfo.cpp
b/lib/Target/ARM64/ARM64TargetTransformInfo.cpp
index f12d1be81a16c9855e96cf110f02e5d5f69fee7d..f41168918099754f2901f061d9290c2011912f3f 100644
(file)
--- a/
lib/Target/ARM64/ARM64TargetTransformInfo.cpp
+++ b/
lib/Target/ARM64/ARM64TargetTransformInfo.cpp
@@
-14,7
+14,6
@@
///
//===----------------------------------------------------------------------===//
///
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "arm64tti"
#include "ARM64.h"
#include "ARM64TargetMachine.h"
#include "MCTargetDesc/ARM64AddressingModes.h"
#include "ARM64.h"
#include "ARM64TargetMachine.h"
#include "MCTargetDesc/ARM64AddressingModes.h"
@@
-25,6
+24,8
@@
#include <algorithm>
using namespace llvm;
#include <algorithm>
using namespace llvm;
+#define DEBUG_TYPE "arm64tti"
+
// Declare the pass initialization routine locally as target-specific passes
// don't havve a target-wide initialization entry point, and so we rely on the
// pass constructor initialization.
// Declare the pass initialization routine locally as target-specific passes
// don't havve a target-wide initialization entry point, and so we rely on the
// pass constructor initialization.
@@
-154,7
+155,7
@@
unsigned ARM64TTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
- if (BitSize == 0
|| BitSize > 128
)
+ if (BitSize == 0)
return ~0U;
// Sign-extend all constants to a multiple of 64-bit.
return ~0U;
// Sign-extend all constants to a multiple of 64-bit.
@@
-179,8
+180,10
@@
unsigned ARM64TTI::getIntImmCost(unsigned Opcode, unsigned Idx,
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
- if (BitSize == 0 || BitSize > 128)
- return ~0U;
+ // There is no cost model for constants with a bit size of 0. Return TCC_Free
+ // here, so that constant hoisting will ignore this constant.
+ if (BitSize == 0)
+ return TCC_Free;
unsigned ImmIdx = ~0U;
switch (Opcode) {
unsigned ImmIdx = ~0U;
switch (Opcode) {
@@
-201,15
+204,19
@@
unsigned ARM64TTI::getIntImmCost(unsigned Opcode, unsigned Idx,
case Instruction::SDiv:
case Instruction::URem:
case Instruction::SRem:
case Instruction::SDiv:
case Instruction::URem:
case Instruction::SRem:
- case Instruction::Shl:
- case Instruction::LShr:
- case Instruction::AShr:
case Instruction::And:
case Instruction::Or:
case Instruction::Xor:
case Instruction::ICmp:
ImmIdx = 1;
break;
case Instruction::And:
case Instruction::Or:
case Instruction::Xor:
case Instruction::ICmp:
ImmIdx = 1;
break;
+ // Always return TCC_Free for the shift value of a shift instruction.
+ case Instruction::Shl:
+ case Instruction::LShr:
+ case Instruction::AShr:
+ if (Idx == 1)
+ return TCC_Free;
+ break;
case Instruction::Trunc:
case Instruction::ZExt:
case Instruction::SExt:
case Instruction::Trunc:
case Instruction::ZExt:
case Instruction::SExt:
@@
-238,8
+245,10
@@
unsigned ARM64TTI::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
- if (BitSize == 0 || BitSize > 128)
- return ~0U;
+ // There is no cost model for constants with a bit size of 0. Return TCC_Free
+ // here, so that constant hoisting will ignore this constant.
+ if (BitSize == 0)
+ return TCC_Free;
switch (IID) {
default:
switch (IID) {
default:
@@
-308,6
+317,10
@@
unsigned ARM64TTI::getCastInstrCost(unsigned Opcode, Type *Dst,
{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 },
{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 },
{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 },
{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 },
+ { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 4 },
+ { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 4 },
+ { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 },
+ { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 4 },
{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 4 },
{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 4 },
};
{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 4 },
{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 4 },
};