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Allow load from constant on SPU.
[oota-llvm.git]
/
lib
/
Target
/
MSP430
/
MSP430RegisterInfo.td
diff --git
a/lib/Target/MSP430/MSP430RegisterInfo.td
b/lib/Target/MSP430/MSP430RegisterInfo.td
index 80db8b069af35d7c281a01af5069a8c780a005d2..ab7b59b4eafe1e2c4f59f3143db0cb218df301d7 100644
(file)
--- a/
lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/
lib/Target/MSP430/MSP430RegisterInfo.td
@@
-43,6
+43,9
@@
def R13B : MSP430Reg<13, "r13">;
def R14B : MSP430Reg<14, "r14">;
def R15B : MSP430Reg<15, "r15">;
def R14B : MSP430Reg<14, "r14">;
def R15B : MSP430Reg<15, "r15">;
+def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
+
+let SubRegIndices = [subreg_8bit] in {
def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>;
def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>;
def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>;
def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>;
@@
-59,17
+62,8
@@
def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>;
def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
-
-def subreg_8bit : SubRegIndex {
- let NumberHack = 1;
- let Namespace = "MSP430";
}
}
-def : SubRegSet<subreg_8bit, [PCW, SPW, SRW, CGW, FPW, R5W, R6W, R7W,
- R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
- [PCB, SPB, SRB, CGB, FPB, R5B, R6B, R7B,
- R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
-
def GR8 : RegisterClass<"MSP430", [i8], 8,
// Volatile registers
[R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,
def GR8 : RegisterClass<"MSP430", [i8], 8,
// Volatile registers
[R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,
@@
-85,10
+79,10
@@
def GR8 : RegisterClass<"MSP430", [i8], 8,
GR8Class::iterator
GR8Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
GR8Class::iterator
GR8Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const Target
RegisterInfo *RI = TM.getRegisterInfo
();
+ const Target
FrameLowering *TFI = TM.getFrameLowering
();
// Depending on whether the function uses frame pointer or not, last 5 or 4
// registers on the list above are reserved
// Depending on whether the function uses frame pointer or not, last 5 or 4
// registers on the list above are reserved
- if (
R
I->hasFP(MF))
+ if (
TF
I->hasFP(MF))
return end()-5;
else
return end()-4;
return end()-5;
else
return end()-4;
@@
-112,10
+106,10
@@
def GR16 : RegisterClass<"MSP430", [i16], 16,
GR16Class::iterator
GR16Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
GR16Class::iterator
GR16Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const Target
RegisterInfo *RI = TM.getRegisterInfo
();
+ const Target
FrameLowering *TFI = TM.getFrameLowering
();
// Depending on whether the function uses frame pointer or not, last 5 or 4
// registers on the list above are reserved
// Depending on whether the function uses frame pointer or not, last 5 or 4
// registers on the list above are reserved
- if (
R
I->hasFP(MF))
+ if (
TF
I->hasFP(MF))
return end()-5;
else
return end()-4;
return end()-5;
else
return end()-4;