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Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
[oota-llvm.git]
/
lib
/
Target
/
Mips
/
MipsExpandPseudo.cpp
diff --git
a/lib/Target/Mips/MipsExpandPseudo.cpp
b/lib/Target/Mips/MipsExpandPseudo.cpp
index fcf602d2cde6060b1c48e2fb89fbb880c5bc0d19..baeae97a4f524829f8d333dba994031456bec2c8 100644
(file)
--- a/
lib/Target/Mips/MipsExpandPseudo.cpp
+++ b/
lib/Target/Mips/MipsExpandPseudo.cpp
@@
-1,4
+1,4
@@
-//===-- MipsExpandPseudo.cpp - Expand Pseudo Instructions -----
*- C++ -*
--===//
+//===-- MipsExpandPseudo.cpp - Expand Pseudo Instructions -----
---------
--===//
//
// The LLVM Compiler Infrastructure
//
//
// The LLVM Compiler Infrastructure
//
@@
-64,16
+64,22
@@
bool MipsExpandPseudo::runOnMachineBasicBlock(MachineBasicBlock& MBB) {
const MCInstrDesc& MCid = I->getDesc();
switch(MCid.getOpcode()) {
const MCInstrDesc& MCid = I->getDesc();
switch(MCid.getOpcode()) {
- default:
+ default:
++I;
continue;
++I;
continue;
+ case Mips::SETGP2:
+ // Convert "setgp2 $globalreg, $t9" to "addu $globalreg, $v0, $t9"
+ BuildMI(MBB, I, I->getDebugLoc(), TII->get(Mips::ADDu),
+ I->getOperand(0).getReg())
+ .addReg(Mips::V0).addReg(I->getOperand(1).getReg());
+ break;
case Mips::BuildPairF64:
ExpandBuildPairF64(MBB, I);
break;
case Mips::ExtractElementF64:
ExpandExtractElementF64(MBB, I);
break;
case Mips::BuildPairF64:
ExpandBuildPairF64(MBB, I);
break;
case Mips::ExtractElementF64:
ExpandExtractElementF64(MBB, I);
break;
- }
+ }
// delete original instr
MBB.erase(I++);
// delete original instr
MBB.erase(I++);
@@
-84,12
+90,12
@@
bool MipsExpandPseudo::runOnMachineBasicBlock(MachineBasicBlock& MBB) {
}
void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB,
}
void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB,
- MachineBasicBlock::iterator I) {
+ MachineBasicBlock::iterator I) {
unsigned DstReg = I->getOperand(0).getReg();
unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
DebugLoc dl = I->getDebugLoc();
unsigned DstReg = I->getOperand(0).getReg();
unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
DebugLoc dl = I->getDebugLoc();
- const u
nsigned
* SubReg =
+ const u
int16_t
* SubReg =
TM.getRegisterInfo()->getSubRegisters(DstReg);
// mtc1 Lo, $fp
TM.getRegisterInfo()->getSubRegisters(DstReg);
// mtc1 Lo, $fp
@@
-105,12
+111,12
@@
void MipsExpandPseudo::ExpandExtractElementF64(MachineBasicBlock& MBB,
unsigned N = I->getOperand(2).getImm();
const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
DebugLoc dl = I->getDebugLoc();
unsigned N = I->getOperand(2).getImm();
const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
DebugLoc dl = I->getDebugLoc();
- const u
nsigned
* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg);
+ const u
int16_t
* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg);
BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
}
BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
}
-/// createMipsMipsExpandPseudoPass - Returns a pass that expands pseudo
+/// createMipsMipsExpandPseudoPass - Returns a pass that expands pseudo
/// instrs into real instrs
FunctionPass *llvm::createMipsExpandPseudoPass(MipsTargetMachine &tm) {
return new MipsExpandPseudo(tm);
/// instrs into real instrs
FunctionPass *llvm::createMipsExpandPseudoPass(MipsTargetMachine &tm) {
return new MipsExpandPseudo(tm);