+ case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
+ case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
+ case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
+ case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
+ case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
+ case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
+ case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
+ case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
+ case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
+ case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
+ case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
+ case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
+ case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
+ case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
+ case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
+ case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
+ case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
+ case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
+ case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
+ case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
+ case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
+ case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";