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Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
[oota-llvm.git]
/
lib
/
Target
/
Mips
/
MipsRegisterInfo.cpp
diff --git
a/lib/Target/Mips/MipsRegisterInfo.cpp
b/lib/Target/Mips/MipsRegisterInfo.cpp
index e0ecba223acdd6733256712256b6ec57c1187ad4..f30de449f6d57c24be1e2b45d56652e8c8e9c7e8 100644
(file)
--- a/
lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/
lib/Target/Mips/MipsRegisterInfo.cpp
@@
-13,10
+13,10
@@
#define DEBUG_TYPE "mips-reg-info"
#define DEBUG_TYPE "mips-reg-info"
+#include "MipsRegisterInfo.h"
#include "Mips.h"
#include "MipsAnalyzeImmediate.h"
#include "MipsSubtarget.h"
#include "Mips.h"
#include "MipsAnalyzeImmediate.h"
#include "MipsSubtarget.h"
-#include "MipsRegisterInfo.h"
#include "MipsMachineFunction.h"
#include "llvm/Constants.h"
#include "llvm/Type.h"
#include "MipsMachineFunction.h"
#include "llvm/Constants.h"
#include "llvm/Type.h"
@@
-62,7
+62,7
@@
getCalleeSavedRegs(const MachineFunction *MF) const
return CSR_O32_SaveList;
else if (Subtarget.isABI_N32())
return CSR_N32_SaveList;
return CSR_O32_SaveList;
else if (Subtarget.isABI_N32())
return CSR_N32_SaveList;
-
+
assert(Subtarget.isABI_N64());
return CSR_N64_SaveList;
}
assert(Subtarget.isABI_N64());
return CSR_N64_SaveList;
}
@@
-83,12
+83,12
@@
MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const
BitVector MipsRegisterInfo::
getReservedRegs(const MachineFunction &MF) const {
BitVector MipsRegisterInfo::
getReservedRegs(const MachineFunction &MF) const {
- static const u
nsigned
ReservedCPURegs[] = {
+ static const u
int16_t
ReservedCPURegs[] = {
Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
Mips::SP, Mips::FP, Mips::RA
};
Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
Mips::SP, Mips::FP, Mips::RA
};
- static const u
nsigned
ReservedCPU64Regs[] = {
+ static const u
int16_t
ReservedCPU64Regs[] = {
Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
Mips::SP_64, Mips::FP_64, Mips::RA_64
};
Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
Mips::SP_64, Mips::FP_64, Mips::RA_64
};
@@
-125,9
+125,18
@@
getReservedRegs(const MachineFunction &MF) const {
Reserved.set(Mips::GP_64);
}
Reserved.set(Mips::GP_64);
}
+ // Reserve hardware registers.
+ Reserved.set(Mips::HWR29);
+ Reserved.set(Mips::HWR29_64);
+
return Reserved;
}
return Reserved;
}
+bool
+MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
+ return true;
+}
+
// This function eliminate ADJCALLSTACKDOWN,
// ADJCALLSTACKUP pseudo instructions
void MipsRegisterInfo::
// This function eliminate ADJCALLSTACKDOWN,
// ADJCALLSTACKUP pseudo instructions
void MipsRegisterInfo::
@@
-223,8
+232,7
@@
eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */);
MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */);
MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
- // FIXME: change this when mips goes MC".
- BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
+ MipsFI->setEmitNOAT();
// The first instruction can be a LUi, which is different from other
// instructions (ADDiu, ORI and SLL) in that it does not have a register
// The first instruction can be a LUi, which is different from other
// instructions (ADDiu, ORI and SLL) in that it does not have a register
@@
-245,7
+253,6
@@
eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
FrameReg = ATReg;
Offset = SignExtend64<16>(Inst->ImmOpnd);
FrameReg = ATReg;
Offset = SignExtend64<16>(Inst->ImmOpnd);
- BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
}
MI.getOperand(i).ChangeToRegister(FrameReg, false);
}
MI.getOperand(i).ChangeToRegister(FrameReg, false);