+/// SelectAddr - Given the specified address, return the two operands for a
+/// load/store instruction, and return true if it should be an indexed [r+r]
+/// operation.
+bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
+ SDOperand &Op2) {
+ unsigned imm = 0;
+ if (Addr.getOpcode() == ISD::ADD) {
+ if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
+ Op1 = getI32Imm(Lo16(imm));
+ if (FrameIndexSDNode *FI =
+ dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
+ ++FrameOff;
+ Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
+ } else {
+ Op2 = Select(Addr.getOperand(0));
+ }
+ return false;
+ } else {
+ Op1 = Select(Addr.getOperand(0));
+ Op2 = Select(Addr.getOperand(1));
+ return true; // [r+r]
+ }
+ }
+
+ // Now check if we're dealing with a global, and whether or not we should emit
+ // an optimized load or store for statics.
+ if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) {
+ GlobalValue *GV = GN->getGlobal();
+ if (!GV->hasWeakLinkage() && !GV->isExternal()) {
+ Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
+ if (PICEnabled)
+ Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),
+ Op1);
+ else
+ Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
+ return false;
+ }
+ } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
+ Op1 = getI32Imm(0);
+ Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
+ return false;
+ } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
+ Op1 = Addr;
+ if (PICEnabled)
+ Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
+ else
+ Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
+ return false;
+ }
+ Op1 = getI32Imm(0);
+ Op2 = Select(Addr);
+ return false;
+}
+
+/// SelectCC - Select a comparison of the specified values with the specified
+/// condition code, returning the CR# of the expression.
+SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
+ ISD::CondCode CC) {
+ // Always select the LHS.
+ LHS = Select(LHS);
+
+ // Use U to determine whether the SETCC immediate range is signed or not.
+ if (MVT::isInteger(LHS.getValueType())) {
+ bool U = ISD::isUnsignedIntSetCC(CC);
+ unsigned Imm;
+ if (isIntImmediate(RHS, Imm) &&
+ ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
+ return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
+ LHS, getI32Imm(Lo16(Imm)));
+ return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
+ LHS, Select(RHS));
+ } else if (LHS.getValueType() == MVT::f32) {
+ return CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, Select(RHS));
+ } else {
+ return CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, Select(RHS));
+ }
+}
+
+/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
+/// to Condition.
+static unsigned getBCCForSetCC(ISD::CondCode CC) {
+ switch (CC) {
+ default: assert(0 && "Unknown condition!"); abort();
+ case ISD::SETEQ: return PPC::BEQ;
+ case ISD::SETNE: return PPC::BNE;
+ case ISD::SETULT:
+ case ISD::SETLT: return PPC::BLT;
+ case ISD::SETULE:
+ case ISD::SETLE: return PPC::BLE;
+ case ISD::SETUGT:
+ case ISD::SETGT: return PPC::BGT;
+ case ISD::SETUGE:
+ case ISD::SETGE: return PPC::BGE;
+ }
+ return 0;
+}
+
+/// getCRIdxForSetCC - Return the index of the condition register field
+/// associated with the SetCC condition, and whether or not the field is
+/// treated as inverted. That is, lt = 0; ge = 0 inverted.
+static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
+ switch (CC) {
+ default: assert(0 && "Unknown condition!"); abort();
+ case ISD::SETULT:
+ case ISD::SETLT: Inv = false; return 0;
+ case ISD::SETUGE:
+ case ISD::SETGE: Inv = true; return 0;
+ case ISD::SETUGT:
+ case ISD::SETGT: Inv = false; return 1;
+ case ISD::SETULE:
+ case ISD::SETLE: Inv = true; return 1;
+ case ISD::SETEQ: Inv = false; return 2;
+ case ISD::SETNE: Inv = true; return 2;
+ }
+ return 0;
+}
+
+// Structure used to return the necessary information to codegen an SDIV as
+// a multiply.
+struct ms {
+ int m; // magic number
+ int s; // shift amount
+};
+
+struct mu {
+ unsigned int m; // magic number
+ int a; // add indicator
+ int s; // shift amount
+};
+
+/// magic - calculate the magic numbers required to codegen an integer sdiv as
+/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
+/// or -1.
+static struct ms magic(int d) {
+ int p;
+ unsigned int ad, anc, delta, q1, r1, q2, r2, t;
+ const unsigned int two31 = 0x80000000U;
+ struct ms mag;
+
+ ad = abs(d);
+ t = two31 + ((unsigned int)d >> 31);
+ anc = t - 1 - t%ad; // absolute value of nc
+ p = 31; // initialize p
+ q1 = two31/anc; // initialize q1 = 2p/abs(nc)
+ r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
+ q2 = two31/ad; // initialize q2 = 2p/abs(d)
+ r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
+ do {
+ p = p + 1;
+ q1 = 2*q1; // update q1 = 2p/abs(nc)
+ r1 = 2*r1; // update r1 = rem(2p/abs(nc))
+ if (r1 >= anc) { // must be unsigned comparison
+ q1 = q1 + 1;
+ r1 = r1 - anc;
+ }
+ q2 = 2*q2; // update q2 = 2p/abs(d)
+ r2 = 2*r2; // update r2 = rem(2p/abs(d))
+ if (r2 >= ad) { // must be unsigned comparison
+ q2 = q2 + 1;
+ r2 = r2 - ad;
+ }
+ delta = ad - r2;
+ } while (q1 < delta || (q1 == delta && r1 == 0));
+
+ mag.m = q2 + 1;
+ if (d < 0) mag.m = -mag.m; // resulting magic number
+ mag.s = p - 32; // resulting shift
+ return mag;
+}
+
+/// magicu - calculate the magic numbers required to codegen an integer udiv as
+/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
+static struct mu magicu(unsigned d)
+{
+ int p;
+ unsigned int nc, delta, q1, r1, q2, r2;
+ struct mu magu;
+ magu.a = 0; // initialize "add" indicator
+ nc = - 1 - (-d)%d;
+ p = 31; // initialize p
+ q1 = 0x80000000/nc; // initialize q1 = 2p/nc
+ r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
+ q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
+ r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
+ do {
+ p = p + 1;
+ if (r1 >= nc - r1 ) {
+ q1 = 2*q1 + 1; // update q1
+ r1 = 2*r1 - nc; // update r1
+ }
+ else {
+ q1 = 2*q1; // update q1
+ r1 = 2*r1; // update r1
+ }
+ if (r2 + 1 >= d - r2) {
+ if (q2 >= 0x7FFFFFFF) magu.a = 1;
+ q2 = 2*q2 + 1; // update q2
+ r2 = 2*r2 + 1 - d; // update r2
+ }
+ else {
+ if (q2 >= 0x80000000) magu.a = 1;
+ q2 = 2*q2; // update q2
+ r2 = 2*r2 + 1; // update r2
+ }
+ delta = d - 1 - r2;
+ } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
+ magu.m = q2 + 1; // resulting magic number
+ magu.s = p - 32; // resulting shift
+ return magu;
+}
+
+/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
+/// return a DAG expression to select that will generate the same value by
+/// multiplying by a magic number. See:
+/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
+SDOperand PPC32DAGToDAGISel::BuildSDIVSequence(SDNode *N) {
+ int d = (int)cast<ConstantSDNode>(N->getOperand(1))->getValue();
+ ms magics = magic(d);
+ // Multiply the numerator (operand 0) by the magic value
+ SDOperand Q = CurDAG->getNode(ISD::MULHS, MVT::i32, N->getOperand(0),
+ CurDAG->getConstant(magics.m, MVT::i32));
+ // If d > 0 and m < 0, add the numerator
+ if (d > 0 && magics.m < 0)
+ Q = CurDAG->getNode(ISD::ADD, MVT::i32, Q, N->getOperand(0));
+ // If d < 0 and m > 0, subtract the numerator.
+ if (d < 0 && magics.m > 0)
+ Q = CurDAG->getNode(ISD::SUB, MVT::i32, Q, N->getOperand(0));
+ // Shift right algebraic if shift value is nonzero
+ if (magics.s > 0)
+ Q = CurDAG->getNode(ISD::SRA, MVT::i32, Q,
+ CurDAG->getConstant(magics.s, MVT::i32));
+ // Extract the sign bit and add it to the quotient
+ SDOperand T =
+ CurDAG->getNode(ISD::SRL, MVT::i32, Q, CurDAG->getConstant(31, MVT::i32));
+ return CurDAG->getNode(ISD::ADD, MVT::i32, Q, T);
+}
+
+/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
+/// return a DAG expression to select that will generate the same value by
+/// multiplying by a magic number. See:
+/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
+SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) {
+ unsigned d = (unsigned)cast<ConstantSDNode>(N->getOperand(1))->getValue();
+ mu magics = magicu(d);
+ // Multiply the numerator (operand 0) by the magic value
+ SDOperand Q = CurDAG->getNode(ISD::MULHU, MVT::i32, N->getOperand(0),
+ CurDAG->getConstant(magics.m, MVT::i32));
+ if (magics.a == 0) {
+ return CurDAG->getNode(ISD::SRL, MVT::i32, Q,
+ CurDAG->getConstant(magics.s, MVT::i32));
+ } else {
+ SDOperand NPQ = CurDAG->getNode(ISD::SUB, MVT::i32, N->getOperand(0), Q);
+ NPQ = CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
+ CurDAG->getConstant(1, MVT::i32));
+ NPQ = CurDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
+ return CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
+ CurDAG->getConstant(magics.s-1, MVT::i32));
+ }
+}
+
+SDOperand PPC32DAGToDAGISel::SelectDYNAMIC_STACKALLOC(SDOperand Op) {
+ SDNode *N = Op.Val;
+
+ // FIXME: We are currently ignoring the requested alignment for handling
+ // greater than the stack alignment. This will need to be revisited at some
+ // point. Align = N.getOperand(2);
+ if (!isa<ConstantSDNode>(N->getOperand(2)) ||
+ cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
+ std::cerr << "Cannot allocate stack object with greater alignment than"
+ << " the stack alignment yet!";
+ abort();
+ }
+ SDOperand Chain = Select(N->getOperand(0));
+ SDOperand Amt = Select(N->getOperand(1));
+
+ SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32);
+
+ SDOperand R1Val = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
+ Chain = R1Val.getValue(1);
+
+ // Subtract the amount (guaranteed to be a multiple of the stack alignment)
+ // from the stack pointer, giving us the result pointer.
+ SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Val);
+
+ // Copy this result back into R1.
+ Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result);
+
+ // Copy this result back out of R1 to make sure we're not using the stack
+ // space without decrementing the stack pointer.
+ Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
+
+ // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
+ CodeGenMap[Op.getValue(0)] = Result;
+ CodeGenMap[Op.getValue(1)] = Result.getValue(1);
+ return SDOperand(Result.Val, Op.ResNo);
+}
+
+SDOperand PPC32DAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
+ SDNode *N = Op.Val;
+ SDOperand LHSL = Select(N->getOperand(0));
+ SDOperand LHSH = Select(N->getOperand(1));
+
+ unsigned Imm;
+ bool ME = false, ZE = false;
+ if (isIntImmediate(N->getOperand(3), Imm)) {
+ ME = (signed)Imm == -1;
+ ZE = Imm == 0;
+ }
+
+ std::vector<SDOperand> Result;
+ SDOperand CarryFromLo;
+ if (isIntImmediate(N->getOperand(2), Imm) &&
+ ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
+ // Codegen the low 32 bits of the add. Interestingly, there is no
+ // shifted form of add immediate carrying.
+ CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ LHSL, getI32Imm(Imm));
+ } else {
+ CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
+ LHSL, Select(N->getOperand(2)));
+ }
+ CarryFromLo = CarryFromLo.getValue(1);
+
+ // Codegen the high 32 bits, adding zero, minus one, or the full value
+ // along with the carry flag produced by addc/addic.
+ SDOperand ResultHi;
+ if (ZE)
+ ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
+ else if (ME)
+ ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
+ else
+ ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
+ Select(N->getOperand(3)), CarryFromLo);
+ Result.push_back(CarryFromLo.getValue(0));
+ Result.push_back(ResultHi);
+
+ CodeGenMap[Op.getValue(0)] = Result[0];
+ CodeGenMap[Op.getValue(1)] = Result[1];
+ return Result[Op.ResNo];
+}
+SDOperand PPC32DAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
+ SDNode *N = Op.Val;
+ SDOperand LHSL = Select(N->getOperand(0));
+ SDOperand LHSH = Select(N->getOperand(1));
+ SDOperand RHSL = Select(N->getOperand(2));
+ SDOperand RHSH = Select(N->getOperand(3));
+
+ std::vector<SDOperand> Result;
+ Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
+ RHSL, LHSL));
+ Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
+ Result[0].getValue(1)));
+ CodeGenMap[Op.getValue(0)] = Result[0];
+ CodeGenMap[Op.getValue(1)] = Result[1];
+ return Result[Op.ResNo];
+}
+
+SDOperand PPC32DAGToDAGISel::SelectSETCC(SDOperand Op) {
+ SDNode *N = Op.Val;
+ unsigned Imm;
+ ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+ if (isIntImmediate(N->getOperand(1), Imm)) {
+ // We can codegen setcc op, imm very efficiently compared to a brcond.
+ // Check for those cases here.
+ // setcc op, 0
+ if (Imm == 0) {
+ SDOperand Op = Select(N->getOperand(0));
+ switch (CC) {
+ default: assert(0 && "Unhandled SetCC condition"); abort();
+ case ISD::SETEQ:
+ Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
+ getI32Imm(5), getI32Imm(31));
+ break;
+ case ISD::SETNE: {
+ SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ Op, getI32Imm(~0U));
+ CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
+ break;
+ }
+ case ISD::SETLT:
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
+ getI32Imm(31), getI32Imm(31));
+ break;
+ case ISD::SETGT: {
+ SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
+ T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
+ getI32Imm(31), getI32Imm(31));
+ break;
+ }
+ }
+ return SDOperand(N, 0);
+ } else if (Imm == ~0U) { // setcc op, -1
+ SDOperand Op = Select(N->getOperand(0));
+ switch (CC) {
+ default: assert(0 && "Unhandled SetCC condition"); abort();
+ case ISD::SETEQ:
+ Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ Op, getI32Imm(1));
+ CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
+ CurDAG->getTargetNode(PPC::LI, MVT::i32,
+ getI32Imm(0)),
+ Op.getValue(1));
+ break;
+ case ISD::SETNE: {
+ Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
+ SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ Op, getI32Imm(~0U));
+ CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
+ break;
+ }
+ case ISD::SETLT: {
+ SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
+ getI32Imm(1));
+ SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
+ getI32Imm(31), getI32Imm(31));
+ break;
+ }
+ case ISD::SETGT:
+ Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
+ getI32Imm(31), getI32Imm(31));
+ CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
+ break;
+ }
+ return SDOperand(N, 0);
+ }
+ }
+
+ bool Inv;
+ unsigned Idx = getCRIdxForSetCC(CC, Inv);
+ SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
+ SDOperand IntCR;
+
+ // Force the ccreg into CR7.
+ SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
+
+ std::vector<MVT::ValueType> VTs;
+ VTs.push_back(MVT::Other);
+ VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
+ std::vector<SDOperand> Ops;
+ Ops.push_back(CurDAG->getEntryNode());
+ Ops.push_back(CR7Reg);
+ Ops.push_back(CCReg);
+ CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
+
+ if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
+ IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
+ else
+ IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
+
+ if (!Inv) {
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
+ getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
+ } else {
+ SDOperand Tmp =
+ CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
+ getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
+ CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
+ }
+
+ return SDOperand(N, 0);
+}