-void
-PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, int FrameIdx,
- const TargetRegisterClass *RC) const {
- if (RC == PPC::GPRCRegisterClass) {
- if (SrcReg != PPC::LR) {
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg),
- FrameIdx);
- } else {
- // FIXME: this spills LR immediately to memory in one step. To do this,
- // we use R11, which we know cannot be used in the prolog/epilog. This is
- // a hack.
- BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11),
- FrameIdx);
- }
- } else if (RC == PPC::G8RCRegisterClass) {
- if (SrcReg != PPC::LR8) {
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg),
- FrameIdx);
- } else {
- // FIXME: this spills LR immediately to memory in one step. To do this,
- // we use R11, which we know cannot be used in the prolog/epilog. This is
- // a hack.
- BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11),
- FrameIdx);
- }
- } else if (RC == PPC::F8RCRegisterClass) {
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg),
- FrameIdx);
- } else if (RC == PPC::F4RCRegisterClass) {
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg),
- FrameIdx);
- } else if (RC == PPC::CRRCRegisterClass) {
- // FIXME: We use R0 here, because it isn't available for RA.
- // We need to store the CR in the low 4-bits of the saved value. First,
- // issue a MFCR to save all of the CRBits.
- BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0);
-
- // If the saved register wasn't CR0, shift the bits left so that they are in
- // CR0's slot.
- if (SrcReg != PPC::CR0) {
- unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
- // rlwinm r0, r0, ShiftBits, 0, 31.
- BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
- .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
- }
-
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0),
- FrameIdx);
- } else if (RC == PPC::VRRCRegisterClass) {
- // We don't have indexed addressing for vector loads. Emit:
- // R11 = ADDI FI#
- // Dest = LVX R0, R11
- //
- // FIXME: We use R0 here, because it isn't available for RA.
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
- FrameIdx, 0, 0);
- BuildMI(MBB, MI, TII.get(PPC::STVX))
- .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }