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[PowerPC] Support powerpc64le as a syntax-checking target.
[oota-llvm.git]
/
lib
/
Target
/
PowerPC
/
PPCTargetMachine.cpp
diff --git
a/lib/Target/PowerPC/PPCTargetMachine.cpp
b/lib/Target/PowerPC/PPCTargetMachine.cpp
index b9c703e708dbf1b138c9cc224671a2a6660d2153..9acefe53ce4a30de29b16da2d41ff9bc592135c7 100644
(file)
--- a/
lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/
lib/Target/PowerPC/PPCTargetMachine.cpp
@@
-13,13
+13,13
@@
#include "PPCTargetMachine.h"
#include "PPC.h"
#include "PPCTargetMachine.h"
#include "PPC.h"
-#include "llvm/PassManager.h"
-#include "llvm/MC/MCStreamer.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetOptions.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/PassManager.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Target/TargetOptions.h"
using namespace llvm;
static cl::
using namespace llvm;
static cl::
@@
-30,6
+30,7
@@
extern "C" void LLVMInitializePowerPCTarget() {
// Register the targets
RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
// Register the targets
RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
+ RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
}
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
}
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
@@
-40,7
+41,7
@@
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, is64Bit),
bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, is64Bit),
- D
ataLayout(Subtarget.getTargetData
String()), InstrInfo(*this),
+ D
L(Subtarget.getDataLayout
String()), InstrInfo(*this),
FrameLowering(Subtarget), JITInfo(*this, is64Bit),
TLInfo(*this), TSInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
FrameLowering(Subtarget), JITInfo(*this, is64Bit),
TLInfo(*this), TSInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
@@
-48,6
+49,7
@@
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
// The binutils for the BG/P are too old for CFI.
if (Subtarget.isBGP())
setMCUseCFI(false);
// The binutils for the BG/P are too old for CFI.
if (Subtarget.isBGP())
setMCUseCFI(false);
+ initAsmInfo();
}
void PPC32TargetMachine::anchor() { }
}
void PPC32TargetMachine::anchor() { }
@@
-86,49
+88,67
@@
public:
return getTM<PPCTargetMachine>();
}
return getTM<PPCTargetMachine>();
}
- virtual bool addPreRegAlloc();
+ const PPCSubtarget &getPPCSubtarget() const {
+ return *getPPCTargetMachine().getSubtargetImpl();
+ }
+
+ virtual bool addPreISel();
+ virtual bool addILPOpts();
virtual bool addInstSelector();
virtual bool addInstSelector();
+ virtual bool addPreSched2();
virtual bool addPreEmitPass();
};
} // namespace
TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
virtual bool addPreEmitPass();
};
} // namespace
TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
- TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
+ return new PPCPassConfig(this, PM);
+}
- // Override this for PowerPC. Tail merging happily breaks up instruction issue
- // groups, which typically degrades performance.
-
PassConfig->setEnableTailMerge(false
);
+bool PPCPassConfig::addPreISel() {
+ if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+
addPass(createPPCCTRLoops(getPPCTargetMachine())
);
- return
PassConfig
;
+ return
false
;
}
}
-bool PPCPassConfig::addPreRegAlloc() {
- if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
- PM->add(createPPCCTRLoops());
+bool PPCPassConfig::addILPOpts() {
+ if (getPPCSubtarget().hasISEL()) {
+ addPass(&EarlyIfConverterID);
+ return true;
+ }
return false;
}
bool PPCPassConfig::addInstSelector() {
// Install an instruction selector.
return false;
}
bool PPCPassConfig::addInstSelector() {
// Install an instruction selector.
- PM->add(createPPCISelDag(getPPCTargetMachine()));
+ addPass(createPPCISelDag(getPPCTargetMachine()));
+
+#ifndef NDEBUG
+ if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+ addPass(createPPCCTRLoopsVerify());
+#endif
+
return false;
}
return false;
}
+bool PPCPassConfig::addPreSched2() {
+ if (getOptLevel() != CodeGenOpt::None)
+ addPass(&IfConverterID);
+
+ return true;
+}
+
bool PPCPassConfig::addPreEmitPass() {
bool PPCPassConfig::addPreEmitPass() {
+ if (getOptLevel() != CodeGenOpt::None)
+ addPass(createPPCEarlyReturnPass());
// Must run branch selection immediately preceding the asm printer.
// Must run branch selection immediately preceding the asm printer.
-
PM->add
(createPPCBranchSelectionPass());
+
addPass
(createPPCBranchSelectionPass());
return false;
}
bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE) {
return false;
}
bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE) {
- // FIXME: This should be moved to TargetJITInfo!!
- if (Subtarget.isPPC64())
- // Temporary workaround for the inability of PPC64 JIT to handle jump
- // tables.
- Options.DisableJumpTables = true;
-
// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
// writing?
Subtarget.SetJITMode();
// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
// writing?
Subtarget.SetJITMode();
@@
-138,3
+158,12
@@
bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
return false;
}
return false;
}
+
+void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
+ // Add first the target-independent BasicTTI pass, then our PPC pass. This
+ // allows the PPC pass to delegate to the target independent layer when
+ // appropriate.
+ PM.add(createBasicTargetTransformInfoPass(this));
+ PM.add(createPPCTargetTransformInfoPass(this));
+}
+