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[X86][Haswell][SchedModel] Add architecture specific scheduling models.
[oota-llvm.git]
/
lib
/
Target
/
README.txt
diff --git
a/lib/Target/README.txt
b/lib/Target/README.txt
index 8165f5b8cc97047216f32b5f6d681e022b2b4310..f4338961718f625330bce51e056dad9ca5bee35c 100644
(file)
--- a/
lib/Target/README.txt
+++ b/
lib/Target/README.txt
@@
-262,22
+262,7
@@
unsigned countbits_slow(unsigned v) {
c += v & 1;
return c;
}
c += v & 1;
return c;
}
-unsigned countbits_fast(unsigned v){
- unsigned c;
- for (c = 0; v; c++)
- v &= v - 1; // clear the least significant bit set
- return c;
-}
-BITBOARD = unsigned long long
-int PopCnt(register BITBOARD a) {
- register int c=0;
- while(a) {
- c++;
- a &= a - 1;
- }
- return c;
-}
unsigned int popcount(unsigned int input) {
unsigned int count = 0;
for (unsigned int i = 0; i < 4 * 8; i++)
unsigned int popcount(unsigned int input) {
unsigned int count = 0;
for (unsigned int i = 0; i < 4 * 8; i++)
@@
-1178,7
+1163,7
@@
There are many load PRE testcases in testsuite/gcc.dg/tree-ssa/loadpre* in the
GCC testsuite, ones we don't get yet are (checked through loadpre25):
[CRIT EDGE BREAKING]
GCC testsuite, ones we don't get yet are (checked through loadpre25):
[CRIT EDGE BREAKING]
-
loadpre3.c
predcom-4.c
+predcom-4.c
[PRE OF READONLY CALL]
loadpre5.c
[PRE OF READONLY CALL]
loadpre5.c