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Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
[oota-llvm.git]
/
lib
/
Target
/
SystemZ
/
SystemZCallingConv.td
diff --git
a/lib/Target/SystemZ/SystemZCallingConv.td
b/lib/Target/SystemZ/SystemZCallingConv.td
index c81decfa8ed6d643d05daece279cacab4e87ad16..c799a9e501aa285f08f397bc0f60ed5d81151e9e 100644
(file)
--- a/
lib/Target/SystemZ/SystemZCallingConv.td
+++ b/
lib/Target/SystemZ/SystemZCallingConv.td
@@
-17,11
+17,11
@@
def RetCC_SystemZ : CallingConv<[
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
// i64 is returned in register R2
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
// i64 is returned in register R2
- CCIfType<[i64], CCAssignToReg<[R2D]>>,
+ CCIfType<[i64], CCAssignToReg<[R2D
, R3D, R4D, R5D
]>>,
// f32 / f64 are returned in F0
// f32 / f64 are returned in F0
- CCIfType<[f32], CCAssignToReg<[F0S]>>,
- CCIfType<[f64], CCAssignToReg<[F0L]>>
+ CCIfType<[f32], CCAssignToReg<[F0S
, F2S, F4S, F6S
]>>,
+ CCIfType<[f64], CCAssignToReg<[F0L
, F2L, F4L, F6L
]>>
]>;
//===----------------------------------------------------------------------===//
]>;
//===----------------------------------------------------------------------===//