+ // FIXME: Hack to handle "imul <imm>, B" which is an alias for "imul <imm>, B,
+ // B".
+ if (Name.startswith("imul") && Operands.size() == 3 &&
+ static_cast<X86Operand*>(Operands[1])->isImm() &&
+ static_cast<X86Operand*>(Operands.back())->isReg()) {
+ X86Operand *Op = static_cast<X86Operand*>(Operands.back());
+ Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(),
+ Op->getEndLoc()));
+ }
+
+ // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
+ // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
+ // errors, since its encoding is the most compact.
+ if (Name == "sldt" && Operands.size() == 2 &&
+ static_cast<X86Operand*>(Operands[1])->isMem()) {
+ delete Operands[0];
+ Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
+ }
+
+ // The assembler accepts "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as
+ // synonyms. Our tables only have the "<reg>, <mem>" form, so if we see the
+ // other operand order, swap them.
+ if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq"||
+ Name == "xchg")
+ if (Operands.size() == 3 &&
+ static_cast<X86Operand*>(Operands[1])->isMem() &&
+ static_cast<X86Operand*>(Operands[2])->isReg()) {
+ std::swap(Operands[1], Operands[2]);
+ }
+
+ // The assembler accepts "testX <reg>, <mem>" and "testX <mem>, <reg>" as
+ // synonyms. Our tables only have the "<mem>, <reg>" form, so if we see the
+ // other operand order, swap them.
+ if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq"||
+ Name == "test")
+ if (Operands.size() == 3 &&
+ static_cast<X86Operand*>(Operands[1])->isReg() &&
+ static_cast<X86Operand*>(Operands[2])->isMem()) {
+ std::swap(Operands[1], Operands[2]);
+ }
+
+ // The assembler accepts these instructions with no operand as a synonym for
+ // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".
+ if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" ||
+ Name == "faddp" || Name == "fsubp" || Name == "fsubrp" ||
+ Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") &&
+ Operands.size() == 1) {
+ Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
+ NameLoc, NameLoc));
+ }
+
+ // The assembler accepts these instructions with two few operands as a synonym
+ // for taking %st(1),%st(0) or X, %st(0).
+ if ((Name == "fcomi" || Name == "fucomi") && Operands.size() < 3) {
+ if (Operands.size() == 1)
+ Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
+ NameLoc, NameLoc));
+ Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
+ NameLoc, NameLoc));
+ }
+
+ // The assembler accepts various amounts of brokenness for fnstsw.
+ if (Name == "fnstsw") {
+ if (Operands.size() == 2 &&
+ static_cast<X86Operand*>(Operands[1])->isReg()) {
+ // "fnstsw al" and "fnstsw eax" -> "fnstw"
+ unsigned Reg = static_cast<X86Operand*>(Operands[1])->Reg.RegNo;
+ if (Reg == MatchRegisterName("eax") ||
+ Reg == MatchRegisterName("al")) {
+ delete Operands[1];
+ Operands.pop_back();
+ }
+ }
+
+ // "fnstw" -> "fnstw %ax"
+ if (Operands.size() == 1)
+ Operands.push_back(X86Operand::CreateReg(MatchRegisterName("ax"),
+ NameLoc, NameLoc));
+ }
+
+ // jmp $42,$5 -> ljmp, similarly for call.
+ if ((Name.startswith("call") || Name.startswith("jmp")) &&
+ Operands.size() == 3 &&
+ static_cast<X86Operand*>(Operands[1])->isImm() &&
+ static_cast<X86Operand*>(Operands[2])->isImm()) {
+ const char *NewOpName = StringSwitch<const char *>(Name)
+ .Case("jmp", "ljmp")
+ .Case("jmpw", "ljmpw")
+ .Case("jmpl", "ljmpl")
+ .Case("jmpq", "ljmpq")
+ .Case("call", "lcall")
+ .Case("callw", "lcallw")
+ .Case("calll", "lcalll")
+ .Case("callq", "lcallq")
+ .Default(0);
+ if (NewOpName) {
+ delete Operands[0];
+ Operands[0] = X86Operand::CreateToken(NewOpName, NameLoc);
+ Name = NewOpName;
+ }
+ }
+
+ // lcall and ljmp -> lcalll and ljmpl
+ if ((Name == "lcall" || Name == "ljmp") && Operands.size() == 3) {
+ delete Operands[0];
+ Operands[0] = X86Operand::CreateToken(Name == "lcall" ? "lcalll" : "ljmpl",
+ NameLoc);
+ }
+
+ // movsd -> movsl (when no operands are specified).
+ if (Name == "movsd" && Operands.size() == 1) {
+ delete Operands[0];
+ Operands[0] = X86Operand::CreateToken("movsl", NameLoc);
+ }
+
+ // fstp <mem> -> fstps <mem>. Without this, we'll default to fstpl due to
+ // suffix searching.
+ if (Name == "fstp" && Operands.size() == 2 &&
+ static_cast<X86Operand*>(Operands[1])->isMem()) {
+ delete Operands[0];
+ Operands[0] = X86Operand::CreateToken("fstps", NameLoc);
+ }
+