+ }
+
+ case X86II::MRMDestMem: {
+ // These instructions are the same as MRMDestReg, but instead of having a
+ // register reference for the mod/rm field, it's a memory reference.
+ //
+ assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
+ isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
+
+ O << getName(MI->getOpCode()) << " <SIZE> PTR ";
+ printMemReference(O, MI, 0, RI);
+ O << ", ";
+ printOp(O, MI->getOperand(4), RI);
+ O << "\n";
+ return;
+ }
+
+ case X86II::MRMSrcReg: {
+ // There is a two forms that are acceptable for MRMSrcReg instructions,
+ // those with 3 and 2 operands:
+ //
+ // 3 Operands: in this form, the last register (the second input) is the
+ // ModR/M input. The first two operands should be the same, post register
+ // allocation. This is for things like: add r32, r/m32
+ //
+ // 2 Operands: this is for things like mov that do not read a second input
+ //
+ assert(isReg(MI->getOperand(0)) &&
+ isReg(MI->getOperand(1)) &&
+ (MI->getNumOperands() == 2 ||
+ (MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
+ && "Bad format for MRMDestReg!");
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+ O << "**";
+
+ O << getName(MI->getOpCode()) << " ";
+ printOp(O, MI->getOperand(0), RI);
+ O << ", ";
+ printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
+ O << "\n";
+ return;
+ }
+
+ case X86II::MRMSrcMem: {
+ // These instructions are the same as MRMSrcReg, but instead of having a
+ // register reference for the mod/rm field, it's a memory reference.
+ //
+ assert(isReg(MI->getOperand(0)) &&
+ (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
+ (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
+ isMem(MI, 2))
+ && "Bad format for MRMDestReg!");
+ if (MI->getNumOperands() == 2+4 &&
+ MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+ O << "**";
+
+ O << getName(MI->getOpCode()) << " ";
+ printOp(O, MI->getOperand(0), RI);
+ O << ", <SIZE> PTR ";
+ printMemReference(O, MI, MI->getNumOperands()-4, RI);
+ O << "\n";
+ return;
+ }
+
+ case X86II::MRMS0r: case X86II::MRMS1r:
+ case X86II::MRMS2r: case X86II::MRMS3r:
+ case X86II::MRMS4r: case X86II::MRMS5r:
+ case X86II::MRMS6r: case X86II::MRMS7r: {
+ // In this form, the following are valid formats:
+ // 1. sete r
+ // 2. cmp reg, immediate
+ // 2. shl rdest, rinput <implicit CL or 1>
+ // 3. sbb rdest, rinput, immediate [rdest = rinput]
+ //
+ assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
+ isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
+ assert((MI->getNumOperands() != 2 ||
+ isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) &&
+ "Bad MRMSxR format!");
+ assert((MI->getNumOperands() < 3 ||
+ (isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) &&
+ "Bad MRMSxR format!");
+
+ if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) &&
+ MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+ O << "**";
+
+ O << getName(MI->getOpCode()) << " ";
+ printOp(O, MI->getOperand(0), RI);
+ if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
+ O << ", ";
+ printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
+ }
+ O << "\n";
+
+ return;
+ }
+