+ unsigned Opcode = MI->getOpcode();
+ const MachineInstrDescriptor &Desc = get(Opcode);
+
+ if (Opcode == X86::PHI) {
+ printOp(O, MI->getOperand(0), RI);
+ O << " = phi ";
+ for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
+ if (i != 1) O << ", ";
+ O << "[";
+ printOp(O, MI->getOperand(i), RI);
+ O << ", ";
+ printOp(O, MI->getOperand(i+1), RI);
+ O << "]";
+ }
+ O << "\n";
+ return;
+ }
+
+
+ switch (Desc.TSFlags & X86II::FormMask) {
+ case X86II::RawFrm:
+ // The accepted forms of Raw instructions are:
+ // 1. nop - No operand required
+ // 2. jmp foo - PC relative displacement operand
+ //
+ assert(MI->getNumOperands() == 0 ||
+ (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
+ "Illegal raw instruction!");
+ O << getName(MI->getOpCode()) << " ";
+
+ if (MI->getNumOperands() == 1) {
+ printOp(O, MI->getOperand(0), RI);
+ }
+ O << "\n";
+ return;
+
+ case X86II::AddRegFrm: {
+ // There are currently two forms of acceptable AddRegFrm instructions.
+ // Either the instruction JUST takes a single register (like inc, dec, etc),
+ // or it takes a register and an immediate of the same size as the register
+ // (move immediate f.e.). Note that this immediate value might be stored as
+ // an LLVM value, to represent, for example, loading the address of a global
+ // into a register.
+ //
+ assert(MI->getOperand(0).isRegister() &&
+ (MI->getNumOperands() == 1 ||
+ (MI->getNumOperands() == 2 &&
+ (MI->getOperand(1).getVRegValueOrNull() ||
+ MI->getOperand(1).isImmediate()))) &&
+ "Illegal form for AddRegFrm instruction!");
+
+ unsigned Reg = MI->getOperand(0).getReg();
+
+ O << getName(MI->getOpCode()) << " ";
+ printOp(O, MI->getOperand(0), RI);
+ if (MI->getNumOperands() == 2) {
+ O << ", ";
+ printOp(O, MI->getOperand(1), RI);
+ }
+ O << "\n";
+ return;
+ }
+ case X86II::MRMDestReg: {
+ // There are two acceptable forms of MRMDestReg instructions, those with 3
+ // and 2 operands:
+ //
+ // 3 Operands: in this form, the first two registers (the destination, and
+ // the first operand) should be the same, post register allocation. The 3rd
+ // operand is an additional input. This should be for things like add
+ // instructions.
+ //
+ // 2 Operands: this is for things like mov that do not read a second input
+ //
+ assert(MI->getOperand(0).isRegister() &&
+ (MI->getNumOperands() == 2 ||
+ (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
+ MI->getOperand(MI->getNumOperands()-1).isRegister()
+ && "Bad format for MRMDestReg!");
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+ O << "**";
+
+ O << getName(MI->getOpCode()) << " ";
+ printOp(O, MI->getOperand(0), RI);
+ O << ", ";
+ printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
+ O << "\n";
+ return;
+ }
+
+ case X86II::MRMDestMem: {
+ // These instructions are the same as MRMDestReg, but instead of having a
+ // register reference for the mod/rm field, it's a memory reference.
+ //
+ assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
+ MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
+
+ O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
+ printMemReference(O, MI, 0, RI);
+ O << ", ";
+ printOp(O, MI->getOperand(4), RI);
+ O << "\n";
+ return;
+ }
+
+ case X86II::MRMSrcReg: {
+ // There is a two forms that are acceptable for MRMSrcReg instructions,
+ // those with 3 and 2 operands:
+ //
+ // 3 Operands: in this form, the last register (the second input) is the
+ // ModR/M input. The first two operands should be the same, post register
+ // allocation. This is for things like: add r32, r/m32
+ //
+ // 2 Operands: this is for things like mov that do not read a second input
+ //
+ assert(MI->getOperand(0).isRegister() &&
+ MI->getOperand(1).isRegister() &&
+ (MI->getNumOperands() == 2 ||
+ (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
+ && "Bad format for MRMDestReg!");
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+ O << "**";
+
+ O << getName(MI->getOpCode()) << " ";
+ printOp(O, MI->getOperand(0), RI);
+ O << ", ";
+ printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
+ O << "\n";
+ return;
+ }
+
+ case X86II::MRMSrcMem: {
+ // These instructions are the same as MRMSrcReg, but instead of having a
+ // register reference for the mod/rm field, it's a memory reference.
+ //
+ assert(MI->getOperand(0).isRegister() &&
+ (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
+ (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
+ isMem(MI, 2))
+ && "Bad format for MRMDestReg!");
+ if (MI->getNumOperands() == 2+4 &&
+ MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+ O << "**";
+
+ O << getName(MI->getOpCode()) << " ";
+ printOp(O, MI->getOperand(0), RI);
+ O << ", " << sizePtr (Desc) << " ";
+ printMemReference(O, MI, MI->getNumOperands()-4, RI);
+ O << "\n";
+ return;
+ }
+
+ case X86II::MRMS0r: case X86II::MRMS1r:
+ case X86II::MRMS2r: case X86II::MRMS3r:
+ case X86II::MRMS4r: case X86II::MRMS5r:
+ case X86II::MRMS6r: case X86II::MRMS7r: {
+ // In this form, the following are valid formats:
+ // 1. sete r
+ // 2. cmp reg, immediate
+ // 2. shl rdest, rinput <implicit CL or 1>
+ // 3. sbb rdest, rinput, immediate [rdest = rinput]
+ //
+ assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
+ MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
+ assert((MI->getNumOperands() != 2 ||
+ MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
+ "Bad MRMSxR format!");
+ assert((MI->getNumOperands() < 3 ||
+ (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
+ "Bad MRMSxR format!");
+
+ if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
+ MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+ O << "**";
+
+ O << getName(MI->getOpCode()) << " ";
+ printOp(O, MI->getOperand(0), RI);
+ if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
+ O << ", ";
+ printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
+ }
+ O << "\n";
+
+ return;
+ }
+
+ default:
+ O << "\t\t\t-"; MI->print(O, TM); break;
+ }