+/// visitCastInst - Here we have various kinds of copying with or without
+/// sign extension going on.
+void
+ISel::visitCastInst (CastInst &CI)
+{
+ const Type *targetType = CI.getType ();
+ Value *operand = CI.getOperand (0);
+ unsigned int operandReg = getReg (operand);
+ const Type *sourceType = operand->getType ();
+ unsigned int destReg = getReg (CI);
+ //
+ // Currently we handle:
+ //
+ // 1) cast * to bool
+ //
+ // 2) cast {sbyte, ubyte} to {sbyte, ubyte}
+ // cast {short, ushort} to {ushort, short}
+ // cast {int, uint, ptr} to {int, uint, ptr}
+ //
+ // 3) cast {sbyte, ubyte} to {ushort, short}
+ // cast {sbyte, ubyte} to {int, uint, ptr}
+ // cast {short, ushort} to {int, uint, ptr}
+ //
+ // 4) cast {int, uint, ptr} to {short, ushort}
+ // cast {int, uint, ptr} to {sbyte, ubyte}
+ // cast {short, ushort} to {sbyte, ubyte}
+ //
+ // 1) Implement casts to bool by using compare on the operand followed
+ // by set if not zero on the result.
+ if (targetType == Type::BoolTy)
+ {
+ BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0);
+ BuildMI (BB, X86::SETNEr, 1, destReg);
+ return;
+ }
+ // 2) Implement casts between values of the same type class (as determined
+ // by getClass) by using a register-to-register move.
+ unsigned int srcClass = getClass (sourceType);
+ unsigned int targClass = getClass (targetType);
+ static const unsigned regRegMove[] = {
+ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
+ };
+ if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass))
+ {
+ BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg);
+ return;
+ }
+ // 3) Handle cast of SMALLER int to LARGER int using a move with sign
+ // extension or zero extension, depending on whether the source type
+ // was signed.
+ if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass))
+ {
+ static const unsigned ops[] = {
+ X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16,
+ X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16
+ };
+ unsigned srcSigned = sourceType->isSigned ();
+ BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1,
+ destReg).addReg (operandReg);
+ return;
+ }
+ // 4) Handle cast of LARGER int to SMALLER int using a move to EAX
+ // followed by a move out of AX or AL.
+ if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass))
+ {
+ static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
+ BuildMI (BB, regRegMove[srcClass], 1,
+ AReg[srcClass]).addReg (operandReg);
+ BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]);
+ return;
+ }
+ // Anything we haven't handled already, we can't (yet) handle at all.
+ //
+ // FP to integral casts can be handled with FISTP to store onto the
+ // stack while converting to integer, followed by a MOV to load from
+ // the stack into the result register. Integral to FP casts can be
+ // handled with MOV to store onto the stack, followed by a FILD to
+ // load from the stack while converting to FP. For the moment, I
+ // can't quite get straight in my head how to borrow myself some
+ // stack space and write on it. Otherwise, this would be trivial.
+ visitInstruction (CI);
+}
+
+/// visitGetElementPtrInst - I don't know, most programs don't have
+/// getelementptr instructions, right? That means we can put off
+/// implementing this, right? Right. This method emits machine
+/// instructions to perform type-safe pointer arithmetic. I am
+/// guessing this could be cleaned up somewhat to use fewer temporary
+/// registers.
+void
+ISel::visitGetElementPtrInst (GetElementPtrInst &I)
+{
+ Value *basePtr = I.getPointerOperand ();
+ const TargetData &TD = TM.DataLayout;
+ unsigned basePtrReg = getReg (basePtr);
+ unsigned resultReg = getReg (I);
+ const Type *Ty = basePtr->getType();
+ // GEPs have zero or more indices; we must perform a struct access
+ // or array access for each one.
+ for (GetElementPtrInst::op_iterator oi = I.idx_begin (),
+ oe = I.idx_end (); oi != oe; ++oi) {
+ Value *idx = *oi;
+ unsigned nextBasePtrReg = makeAnotherReg ();
+ if (const StructType *StTy = dyn_cast <StructType> (Ty)) {
+ // It's a struct access. idx is the index into the structure,
+ // which names the field. This index must have ubyte type.
+ const ConstantUInt *CUI = cast <ConstantUInt> (idx);
+ assert (CUI->getType () == Type::UByteTy
+ && "Funny-looking structure index in GEP");
+ // Use the TargetData structure to pick out what the layout of
+ // the structure is in memory. Since the structure index must
+ // be constant, we can get its value and use it to find the
+ // right byte offset from the StructLayout class's list of
+ // structure member offsets.
+ unsigned idxValue = CUI->getValue ();
+ unsigned memberOffset =
+ TD.getStructLayout (StTy)->MemberOffsets[idxValue];
+ // Emit an ADD to add memberOffset to the basePtr.
+ BuildMI (BB, X86::ADDri32, 2,
+ nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
+ // The next type is the member of the structure selected by the
+ // index.
+ Ty = StTy->getElementTypes ()[idxValue];
+ } else if (const SequentialType *SqTy = cast <SequentialType> (Ty)) {
+ // It's an array or pointer access: [ArraySize x ElementType].
+ // The documentation does not seem to match the code on the type
+ // of array indices. The code seems to use long, and the docs
+ // (and the comments) say uint. If it is long, I don't know what
+ // we are going to do, because the X86 loves 64-bit types.
+ const Type *typeOfSequentialTypeIndex = SqTy->getIndexType ();
+ // idx is the index into the array. Unlike with structure
+ // indices, we may not know its actual value at code-generation
+ // time.
+ assert (idx->getType () == typeOfSequentialTypeIndex
+ && "Funny-looking array index in GEP");
+ // We want to add basePtrReg to (idxReg * sizeof
+ // ElementType). First, we must find the size of the pointed-to
+ // type. (Not coincidentally, the next type is the type of the
+ // elements in the array.)
+ Ty = SqTy->getElementType ();
+ unsigned elementSize = TD.getTypeSize (Ty);
+ unsigned elementSizeReg = makeAnotherReg ();
+ copyConstantToRegister (ConstantInt::get (typeOfSequentialTypeIndex,
+ elementSize),
+ elementSizeReg);
+ unsigned idxReg = getReg (idx);
+ // Emit a MUL to multiply the register holding the index by
+ // elementSize, putting the result in memberOffsetReg.
+ unsigned memberOffsetReg = makeAnotherReg ();
+ doMultiply (memberOffsetReg, typeOfSequentialTypeIndex,
+ elementSizeReg, idxReg);
+ // Emit an ADD to add memberOffsetReg to the basePtr.
+ BuildMI (BB, X86::ADDrr32, 2,
+ nextBasePtrReg).addReg (basePtrReg).addReg (memberOffsetReg);
+ }
+ // Now that we are here, further indices refer to subtypes of this
+ // one, so we don't need to worry about basePtrReg itself, anymore.
+ basePtrReg = nextBasePtrReg;
+ }
+ // After we have processed all the indices, the result is left in
+ // basePtrReg. Move it to the register where we were expected to
+ // put the answer. A 32-bit move should do it, because we are in
+ // ILP32 land.
+ BuildMI (BB, X86::MOVrr32, 1, getReg (I)).addReg (basePtrReg);
+}
+
+
+/// visitMallocInst - I know that personally, whenever I want to remember
+/// something, I have to clear off some space in my brain.
+void
+ISel::visitMallocInst (MallocInst &I)
+{
+ visitInstruction (I);
+}
+
+
+/// visitAllocaInst - I want some stack space. Come on, man, I said I
+/// want some freakin' stack space.
+void
+ISel::visitAllocaInst (AllocaInst &I)
+{
+ visitInstruction (I);
+}
+