+/// convertToThreeAddress - This method must be implemented by targets that
+/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
+/// may be able to convert a two-address instruction into a true
+/// three-address instruction on demand. This allows the X86 target (for
+/// example) to convert ADD and SHL instructions into LEA instructions if they
+/// would require register copies due to two-addressness.
+///
+/// This method returns a null pointer if the transformation cannot be
+/// performed, otherwise it returns the new instruction.
+///
+MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
+ // All instructions input are two-addr instructions. Get the known operands.
+ unsigned Dest = MI->getOperand(0).getReg();
+ unsigned Src = MI->getOperand(1).getReg();
+
+ switch (MI->getOpcode()) {
+ default: break;
+ case X86::SHUFPSrri: {
+ assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
+ const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
+ unsigned A = MI->getOperand(0).getReg();
+ unsigned B = MI->getOperand(1).getReg();
+ unsigned C = MI->getOperand(2).getReg();
+ unsigned M = MI->getOperand(3).getImmedValue();
+ if (!Subtarget->hasSSE2() || B != C) return 0;
+ return BuildMI(X86::PSHUFDri, 2, A).addReg(B).addImm(M);
+ }
+ }
+
+ // FIXME: None of these instructions are promotable to LEAs without
+ // additional information. In particular, LEA doesn't set the flags that
+ // add and inc do. :(
+ return 0;
+
+ // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
+ // we have subtarget support, enable the 16-bit LEA generation here.
+ bool DisableLEA16 = true;
+
+ switch (MI->getOpcode()) {
+ case X86::INC32r:
+ assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
+ return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
+ case X86::INC16r:
+ if (DisableLEA16) return 0;
+ assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
+ return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
+ case X86::DEC32r:
+ assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
+ return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
+ case X86::DEC16r:
+ if (DisableLEA16) return 0;
+ assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
+ return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
+ case X86::ADD32rr:
+ assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
+ return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
+ MI->getOperand(2).getReg());
+ case X86::ADD16rr:
+ if (DisableLEA16) return 0;
+ assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
+ return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
+ MI->getOperand(2).getReg());
+ case X86::ADD32ri:
+ case X86::ADD32ri8:
+ assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
+ if (MI->getOperand(2).isImmediate())
+ return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
+ MI->getOperand(2).getImmedValue());
+ return 0;
+ case X86::ADD16ri:
+ case X86::ADD16ri8:
+ if (DisableLEA16) return 0;
+ assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
+ if (MI->getOperand(2).isImmediate())
+ return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
+ MI->getOperand(2).getImmedValue());
+ break;
+
+ case X86::SHL16ri:
+ if (DisableLEA16) return 0;
+ case X86::SHL32ri:
+ assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
+ "Unknown shl instruction!");
+ unsigned ShAmt = MI->getOperand(2).getImmedValue();
+ if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
+ X86AddressMode AM;
+ AM.Scale = 1 << ShAmt;
+ AM.IndexReg = Src;
+ unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
+ return addFullAddress(BuildMI(Opc, 5, Dest), AM);
+ }
+ break;
+ }
+
+ return 0;