-I(SHLrr8 , "shlb", 0, 0) // R8 <<= cl D2/4
-I(SHLir8 , "shlb", 0, 0) // R8 <<= imm8 C0/4 ib
-I(SHLrr16 , "shlw", 0, 0) // R16 <<= cl D3/4
-I(SHLir16 , "shlw", 0, 0) // R16 <<= imm8 C1/4 ib
-I(SHLrr32 , "shll", 0, 0) // R32 <<= cl D3/4
-I(SHLir32 , "shll", 0, 0) // R32 <<= imm8 C1/4 ib
-I(SHRrr8 , "shrb", 0, 0) // R8 >>>= cl D2/5
-I(SHRir8 , "shrb", 0, 0) // R8 >>>= imm8 C0/5 ib
-I(SHRrr16 , "shrw", 0, 0) // R16 >>>= cl D3/5
-I(SHRir16 , "shrw", 0, 0) // R16 >>>= imm8 C1/5 ib
-I(SHRrr32 , "shrl", 0, 0) // R32 >>>= cl D3/5
-I(SHRir32 , "shrl", 0, 0) // R32 >>>= imm8 C1/5 ib
-I(SARrr8 , "sarb", 0, 0) // R8 >>= cl D2/7
-I(SARir8 , "sarb", 0, 0) // R8 >>= imm8 C0/7 ib
-I(SARrr16 , "sarw", 0, 0) // R16 >>= cl D3/7
-I(SARir16 , "sarw", 0, 0) // R16 >>= imm8 C1/7 ib
-I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7
-I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib
+I(SHLrr8 , "shlb", 0xD2, 0, X86II::MRMS4r, O_CL, NoImpRegs) // R8 <<= cl D2/4
+I(SHLrr16 , "shlw", 0xD3, 0, X86II::MRMS4r | X86II::OpSize, O_CL, NoImpRegs) // R16 <<= cl D3/4
+I(SHLrr32 , "shll", 0xD3, 0, X86II::MRMS4r, O_CL, NoImpRegs) // R32 <<= cl D3/4
+I(SHLir8 , "shlb", 0xC0, 0, X86II::MRMS4r, NoImpRegs, NoImpRegs) // R8 <<= imm8 C0/4 ib
+I(SHLir16 , "shlw", 0xC1, 0, X86II::MRMS4r | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 <<= imm8 C1/4 ib
+I(SHLir32 , "shll", 0xC1, 0, X86II::MRMS4r, NoImpRegs, NoImpRegs) // R32 <<= imm8 C1/4 ib
+I(SHRrr8 , "shrb", 0xD2, 0, X86II::MRMS5r, O_CL, NoImpRegs) // R8 >>>= cl D2/5
+I(SHRrr16 , "shrw", 0xD3, 0, X86II::MRMS5r | X86II::OpSize, O_CL, NoImpRegs) // R16 >>>= cl D3/5
+I(SHRrr32 , "shrl", 0xD3, 0, X86II::MRMS5r, O_CL, NoImpRegs) // R32 >>>= cl D3/5
+I(SHRir8 , "shrb", 0xC0, 0, X86II::MRMS5r, NoImpRegs, NoImpRegs) // R8 >>>= imm8 C0/5 ib
+I(SHRir16 , "shrw", 0xC1, 0, X86II::MRMS5r | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 >>>= imm8 C1/5 ib
+I(SHRir32 , "shrl", 0xC1, 0, X86II::MRMS5r, NoImpRegs, NoImpRegs) // R32 >>>= imm8 C1/5 ib
+I(SARrr8 , "sarb", 0xD2, 0, X86II::MRMS7r, O_CL, NoImpRegs) // R8 >>= cl D2/7
+I(SARrr16 , "sarw", 0xD3, 0, X86II::MRMS7r | X86II::OpSize, O_CL, NoImpRegs) // R16 >>= cl D3/7
+I(SARrr32 , "sarl", 0xD3, 0, X86II::MRMS7r, O_CL, NoImpRegs) // R32 >>= cl D3/7
+I(SARir8 , "sarb", 0xC0, 0, X86II::MRMS7r, NoImpRegs, NoImpRegs) // R8 >>= imm8 C0/7 ib
+I(SARir16 , "sarw", 0xC1, 0, X86II::MRMS7r | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 >>= imm8 C1/7 ib
+I(SARir32 , "sarl", 0xC1, 0, X86II::MRMS7r, NoImpRegs, NoImpRegs) // R32 >>= imm8 C1/7 ib