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AMDGPU: Fix printing trailing whitespace for mubuf atomics
[oota-llvm.git]
/
lib
/
Target
/
XCore
/
XCoreISelLowering.h
diff --git
a/lib/Target/XCore/XCoreISelLowering.h
b/lib/Target/XCore/XCoreISelLowering.h
index 8d258f5054c1b2d1f63600fdacccb5effae6b7d9..ddd675c5164d766e19075d17ca577612a3a40fef 100644
(file)
--- a/
lib/Target/XCore/XCoreISelLowering.h
+++ b/
lib/Target/XCore/XCoreISelLowering.h
@@
-12,8
+12,8
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#ifndef XCOREISELLOWERING_H
-#define XCOREISELLOWERING_H
+#ifndef
LLVM_LIB_TARGET_XCORE_
XCOREISELLOWERING_H
+#define
LLVM_LIB_TARGET_XCORE_
XCOREISELLOWERING_H
#include "XCore.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "XCore.h"
#include "llvm/CodeGen/SelectionDAG.h"
@@
-26,7
+26,7
@@
namespace llvm {
class XCoreTargetMachine;
namespace XCoreISD {
class XCoreTargetMachine;
namespace XCoreISD {
- enum NodeType {
+ enum NodeType
: unsigned
{
// Start the numbering where the builtin ops and target ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END,
// Start the numbering where the builtin ops and target ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END,
@@
-42,6
+42,9
@@
namespace llvm {
// cp relative address
CPRelativeWrapper,
// cp relative address
CPRelativeWrapper,
+ // Load word from stack
+ LDWSP,
+
// Store word to stack
STWSP,
// Store word to stack
STWSP,
@@
-70,7
+73,17
@@
namespace llvm {
BR_JT,
// Jumptable branch using long branches for each entry.
BR_JT,
// Jumptable branch using long branches for each entry.
- BR_JT32
+ BR_JT32,
+
+ // Offset from frame pointer to the first (possible) on-stack argument
+ FRAME_TO_ARGS_OFFSET,
+
+ // Exception handler return. The stack is restored to the first
+ // followed by a jump to the second argument.
+ EH_RETURN,
+
+ // Memory barrier.
+ MEMBARRIER
};
}
};
}
@@
-80,34
+93,40
@@
namespace llvm {
class XCoreTargetLowering : public TargetLowering
{
public:
class XCoreTargetLowering : public TargetLowering
{
public:
+ explicit XCoreTargetLowering(const TargetMachine &TM,
+ const XCoreSubtarget &Subtarget);
- explicit XCoreTargetLowering(XCoreTargetMachine &TM);
+ using TargetLowering::isZExtFree;
+ bool isZExtFree(SDValue Val, EVT VT2) const override;
- virtual unsigned getJumpTableEncoding() const;
- virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
+
+ unsigned getJumpTableEncoding() const override;
+ MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override {
+ return MVT::i32;
+ }
/// LowerOperation - Provide custom lowering hooks for some operations.
/// LowerOperation - Provide custom lowering hooks for some operations.
-
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
;
+
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
;
/// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code.
///
/// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code.
///
- v
irtual v
oid ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
-
SelectionDAG &DAG) const
;
+ void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
+
SelectionDAG &DAG) const override
;
/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
-
virtual const char *getTargetNodeName(unsigned Opcode) const
;
+
const char *getTargetNodeName(unsigned Opcode) const override
;
-
virtual
MachineBasicBlock *
+ MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI,
EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *MBB) const;
+ MachineBasicBlock *MBB) const
override
;
-
virtual bool isLegalAddressingMode(
const AddrMode &AM,
-
Type *Ty) const
;
+
bool isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM,
+
Type *Ty, unsigned AS) const override
;
private:
private:
- const
XCore
TargetMachine &TM;
+ const TargetMachine &TM;
const XCoreSubtarget &Subtarget;
// Lower Operand helpers
const XCoreSubtarget &Subtarget;
// Lower Operand helpers
@@
-115,7
+134,7
@@
namespace llvm {
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
-
Debug
Loc dl, SelectionDAG &DAG,
+
SD
Loc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg,
SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg,
@@
-123,77
+142,80
@@
namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
-
Debug
Loc dl, SelectionDAG &DAG,
+
SD
Loc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
SmallVectorImpl<SDValue> &InVals) const;
- SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
- CallingConv::ID CallConv, bool isVarArg,
- const SmallVectorImpl<ISD::InputArg> &Ins,
- DebugLoc dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) const;
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
SelectionDAG &DAG) const;
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
SelectionDAG &DAG) const;
+ SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
+ SDValue Base, int64_t Offset,
+ SelectionDAG &DAG) const;
// Lower Operand specifics
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
// Lower Operand specifics
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
// Inline asm support
// Inline asm support
- std::pair<unsigned, const TargetRegisterClass*>
- getRegForInlineAsmConstraint(const
std::string &Constraint
,
-
EVT VT) const
;
+ std::pair<unsigned, const TargetRegisterClass
*>
+ getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI
,
+
StringRef Constraint, MVT VT) const override
;
// Expand specifics
SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
// Expand specifics
SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
-
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
;
+
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
;
- v
irtual void computeMasked
BitsForTargetNode(const SDValue Op,
-
APInt &KnownZero,
-
APInt &KnownOne,
-
const SelectionDAG &DAG,
-
unsigned Depth = 0) const
;
+ v
oid computeKnown
BitsForTargetNode(const SDValue Op,
+ APInt &KnownZero,
+ APInt &KnownOne,
+ const SelectionDAG &DAG,
+
unsigned Depth = 0) const override
;
-
virtual
SDValue
+ SDValue
LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
-
Debug
Loc dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) const;
+
SD
Loc dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const
override
;
-
virtual
SDValue
+ SDValue
LowerCall(TargetLowering::CallLoweringInfo &CLI,
LowerCall(TargetLowering::CallLoweringInfo &CLI,
- SmallVectorImpl<SDValue> &InVals) const;
+ SmallVectorImpl<SDValue> &InVals) const
override
;
-
virtual
SDValue
+ SDValue
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
-
DebugLoc dl, SelectionDAG &DAG) const
;
+
SDLoc dl, SelectionDAG &DAG) const override
;
-
virtual
bool
+ bool
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
- LLVMContext &Context) const;
+ LLVMContext &Context) const
override
;
};
}
};
}
-#endif
// XCOREISELLOWERING_H
+#endif