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ARM64: firefly: Add rk3399-firefly board support
[firefly-linux-kernel-4.4.55.git]
/
sound
/
soc
/
codecs
/
rt5640.h
diff --git
a/sound/soc/codecs/rt5640.h
b/sound/soc/codecs/rt5640.h
index 3deb8babeabb691d37a314bb3ab19c84d5c9cd1f..e7ab4093b61f4344566ef20fcc612b14d4ada876 100644
(file)
--- a/
sound/soc/codecs/rt5640.h
+++ b/
sound/soc/codecs/rt5640.h
@@
-12,6
+12,7
@@
#ifndef _RT5640_H
#define _RT5640_H
#ifndef _RT5640_H
#define _RT5640_H
+#include <linux/clk.h>
#include <sound/rt5640.h>
/* Info */
#include <sound/rt5640.h>
/* Info */
@@
-177,6
+178,8
@@
#define RT5640_EQ_GN_HIP2 0xb2
#define RT5640_EQ_PRE_VOL 0xb3
#define RT5640_EQ_PST_VOL 0xb4
#define RT5640_EQ_GN_HIP2 0xb2
#define RT5640_EQ_PRE_VOL 0xb3
#define RT5640_EQ_PST_VOL 0xb4
+/* General Control */
+#define RT5640_GEN_CTRL1 0xfa
/* global definition */
#define RT5640_L_MUTE (0x1 << 15)
/* global definition */
#define RT5640_L_MUTE (0x1 << 15)
@@
-442,39
+445,39
@@
#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
#define RT5640_IF1_DAC_SEL_SFT 14
#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
#define RT5640_IF1_DAC_SEL_SFT 14
#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
-#define RT5640_IF1_DAC_SEL_
L2R
(0x1 << 14)
-#define RT5640_IF1_DAC_SEL_
R2L
(0x2 << 14)
-#define RT5640_IF1_DAC_SEL_
SWAP
(0x3 << 14)
+#define RT5640_IF1_DAC_SEL_
SWAP
(0x1 << 14)
+#define RT5640_IF1_DAC_SEL_
L2R
(0x2 << 14)
+#define RT5640_IF1_DAC_SEL_
R2L
(0x3 << 14)
#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
#define RT5640_IF1_ADC_SEL_SFT 12
#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
#define RT5640_IF1_ADC_SEL_SFT 12
#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
-#define RT5640_IF1_ADC_SEL_
L2R
(0x1 << 12)
-#define RT5640_IF1_ADC_SEL_
R2L
(0x2 << 12)
-#define RT5640_IF1_ADC_SEL_
SWAP
(0x3 << 12)
+#define RT5640_IF1_ADC_SEL_
SWAP
(0x1 << 12)
+#define RT5640_IF1_ADC_SEL_
L2R
(0x2 << 12)
+#define RT5640_IF1_ADC_SEL_
R2L
(0x3 << 12)
#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
#define RT5640_IF2_DAC_SEL_SFT 10
#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
#define RT5640_IF2_DAC_SEL_SFT 10
#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
-#define RT5640_IF2_DAC_SEL_
L2R
(0x1 << 10)
-#define RT5640_IF2_DAC_SEL_
R2L
(0x2 << 10)
-#define RT5640_IF2_DAC_SEL_
SWAP
(0x3 << 10)
+#define RT5640_IF2_DAC_SEL_
SWAP
(0x1 << 10)
+#define RT5640_IF2_DAC_SEL_
L2R
(0x2 << 10)
+#define RT5640_IF2_DAC_SEL_
R2L
(0x3 << 10)
#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
#define RT5640_IF2_ADC_SEL_SFT 8
#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
#define RT5640_IF2_ADC_SEL_SFT 8
#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
-#define RT5640_IF2_ADC_SEL_
L2R
(0x1 << 8)
-#define RT5640_IF2_ADC_SEL_
R2L
(0x2 << 8)
-#define RT5640_IF2_ADC_SEL_
SWAP
(0x3 << 8)
+#define RT5640_IF2_ADC_SEL_
SWAP
(0x1 << 8)
+#define RT5640_IF2_ADC_SEL_
L2R
(0x2 << 8)
+#define RT5640_IF2_ADC_SEL_
R2L
(0x3 << 8)
#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
#define RT5640_IF3_DAC_SEL_SFT 6
#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
#define RT5640_IF3_DAC_SEL_SFT 6
#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
-#define RT5640_IF3_DAC_SEL_
L2R
(0x1 << 6)
-#define RT5640_IF3_DAC_SEL_
R2L
(0x2 << 6)
-#define RT5640_IF3_DAC_SEL_
SWAP
(0x3 << 6)
+#define RT5640_IF3_DAC_SEL_
SWAP
(0x1 << 6)
+#define RT5640_IF3_DAC_SEL_
L2R
(0x2 << 6)
+#define RT5640_IF3_DAC_SEL_
R2L
(0x3 << 6)
#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
#define RT5640_IF3_ADC_SEL_SFT 4
#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)
#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
#define RT5640_IF3_ADC_SEL_SFT 4
#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)
-#define RT5640_IF3_ADC_SEL_
L2R
(0x1 << 4)
-#define RT5640_IF3_ADC_SEL_
R2L
(0x2 << 4)
-#define RT5640_IF3_ADC_SEL_
SWAP
(0x3 << 4)
+#define RT5640_IF3_ADC_SEL_
SWAP
(0x1 << 4)
+#define RT5640_IF3_ADC_SEL_
L2R
(0x2 << 4)
+#define RT5640_IF3_ADC_SEL_
R2L
(0x3 << 4)
/* REC Left Mixer Control 1 (0x3b) */
#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
/* REC Left Mixer Control 1 (0x3b) */
#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
@@
-2035,6
+2038,10
@@
enum {
#define RT5640_HEADSET_DET BIT(1)
#define RT5640_HEADPHO_DET BIT(2)
#define RT5640_HEADSET_DET BIT(1)
#define RT5640_HEADPHO_DET BIT(2)
+/* General Control1 (0xfa) */
+#define RT5640_M_MAMIX_L (0x1 << 13)
+#define RT5640_M_MAMIX_R (0x1 << 12)
+
/* System Clock Source */
#define RT5640_SCLK_S_MCLK 0
#define RT5640_SCLK_S_PLL1 1
/* System Clock Source */
#define RT5640_SCLK_S_MCLK 0
#define RT5640_SCLK_S_PLL1 1
@@
-2083,6
+2090,7
@@
struct rt5640_priv {
struct snd_soc_codec *codec;
struct rt5640_platform_data pdata;
struct regmap *regmap;
struct snd_soc_codec *codec;
struct rt5640_platform_data pdata;
struct regmap *regmap;
+ struct clk *mclk;
int sysclk;
int sysclk_src;
int sysclk;
int sysclk_src;
@@
-2095,6
+2103,14
@@
struct rt5640_priv {
int pll_out;
bool hp_mute;
int pll_out;
bool hp_mute;
+
+ struct delayed_work adc_poll_work;
+ struct iio_channel *chan;
+ int hp_det_adc_value;
+ bool hp_insert;
+ int hp_con_gpio;
+ bool hp_con_gpio_active_high;
+ struct snd_soc_jack hp_jack;
};
int rt5640_dmic_enable(struct snd_soc_codec *codec,
};
int rt5640_dmic_enable(struct snd_soc_codec *codec,