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R600/SI: Move instruction patterns to scalar versions.
[oota-llvm.git]
/
test
/
CodeGen
/
R600
/
llvm.sin.ll
diff --git
a/test/CodeGen/R600/llvm.sin.ll
b/test/CodeGen/R600/llvm.sin.ll
index 803dc2d6debc083d67ddd9b2731161590374c113..9eb998315fef7d4deaaa06f034f4c16c5fcd1d36 100644
(file)
--- a/
test/CodeGen/R600/llvm.sin.ll
+++ b/
test/CodeGen/R600/llvm.sin.ll
@@
-1,16
+1,19
@@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: SIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MULADD_IEEE *
+;CHECK: FRACT *
+;CHECK: ADD *
+;CHECK: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-define void @test(
)
{
- %r0 =
call float @llvm.R600.load.input(i32 0)
+define void @test(
<4 x float> inreg %reg0) #0
{
+ %r0 =
extractelement <4 x float> %reg0, i32 0
%r1 = call float @llvm.sin.f32( float %r0)
%r1 = call float @llvm.sin.f32( float %r0)
- call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+ %vec = insertelement <4 x float> undef, float %r1, i32 0
+ call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
declare float @llvm.sin.f32(float) readnone
ret void
}
declare float @llvm.sin.f32(float) readnone
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-declare float @llvm.R600.load.input(i32) readnone
-
-declare void @llvm.AMDGPU.store.output(float, i32)
+attributes #0 = { "ShaderType"="0" }