- if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
- // Is the operand continuous? If so, we can just mask and OR it in
- // instead of doing it bit-by-bit, saving a lot in runtime cost.
- const BitsInit *InstInit = BI;
- int beginBitInVar = -1, endBitInVar = -1;
- int beginBitInInst = -1, endBitInInst = -1;
- bool continuous = true;
-
- for (int bit = InstInit->getNumBits()-1; bit >= 0; --bit) {
- if (VarBitInit *VBI =
- dynamic_cast<VarBitInit*>(InstInit->getBit(bit))) {
- TypedInit *TI = VBI->getVariable();
- if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
- // only process the current variable
- if (VI->getName() != Vals[i].getName())
- continue;
-
- if (beginBitInVar == -1)
- beginBitInVar = VBI->getBitNum();
-
- if (endBitInVar == -1)
- endBitInVar = VBI->getBitNum();
- else {
- if (endBitInVar == (int)VBI->getBitNum() + 1)
- endBitInVar = VBI->getBitNum();
- else {
- continuous = false;
- break;
- }
- }
-
- if (beginBitInInst == -1)
- beginBitInInst = bit;
- if (endBitInInst == -1)
- endBitInInst = bit;
- else {
- if (endBitInInst == bit + 1)
- endBitInInst = bit;
- else {
- continuous = false;
- break;
- }
- }
-
- // maintain same distance between bits in field and bits in
- // instruction. if the relative distances stay the same
- // throughout,
- if (beginBitInVar - (int)VBI->getBitNum() !=
- beginBitInInst - bit) {
- continuous = false;
- break;
- }
- }
- }
- }
-
- // If we have found no bit in "Inst" which comes from this field, then
- // this is not an operand!!
- if (beginBitInInst != -1) {
- o << " // op" << op << ": " << Vals[i].getName() << "\n"
- << " int64_t op" << op
- <<" = getMachineOpValue(MI, MI.getOperand("<<op<<"));\n";
- //<< " MachineOperand &op" << op <<" = MI.getOperand("<<op<<");\n";
- OpOrder[Vals[i].getName()] = op++;
-
- DEBUG(o << " // Var: begin = " << beginBitInVar
- << ", end = " << endBitInVar
- << "; Inst: begin = " << beginBitInInst
- << ", end = " << endBitInInst << "\n");
-
- if (continuous) {
- DEBUG(o << " // continuous: op" << OpOrder[Vals[i].getName()]
- << "\n");
-
- // Mask off the right bits
- // Low mask (ie. shift, if necessary)
- assert(endBitInVar >= 0 && "Negative shift amount in masking!");
- if (endBitInVar != 0) {
- o << " op" << OpOrder[Vals[i].getName()]
- << " >>= " << endBitInVar << ";\n";
- beginBitInVar -= endBitInVar;
- endBitInVar = 0;
- }
-
- // High mask
- o << " op" << OpOrder[Vals[i].getName()]
- << " &= (1<<" << beginBitInVar+1 << ") - 1;\n";
-
- // Shift the value to the correct place (according to place in inst)
- assert(endBitInInst >= 0 && "Negative shift amount!");
- if (endBitInInst != 0)
- o << " op" << OpOrder[Vals[i].getName()]
- << " <<= " << endBitInInst << ";\n";
-
- // Just OR in the result
- o << " Value |= op" << OpOrder[Vals[i].getName()] << ";\n";
- }
-
- // otherwise, will be taken care of in the loop below using this
- // value:
- OpContinuous[Vals[i].getName()] = continuous;
- }
- }
+ unsigned OpIdx;
+ if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx))
+ continue;
+
+ NamedOpIndices.insert(OpIdx);
+ }
+ }
+
+ // Loop over all of the fields in the instruction, determining which are the
+ // operands to the instruction.
+ for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
+ // Ignore fixed fields in the record, we're looking for values like:
+ // bits<5> RST = { ?, ?, ?, ?, ? };
+ if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
+ continue;
+
+ AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp,
+ NamedOpIndices, Case, Target);
+ }
+
+ std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
+ if (!PostEmitter.empty()) {
+ Case += " Value = " + PostEmitter + "(MI, Value";
+ Case += ", STI";
+ Case += ");\n";
+ }
+
+ return Case;
+}
+
+void CodeEmitterGen::run(raw_ostream &o) {
+ CodeGenTarget Target(Records);
+ std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
+
+ // For little-endian instruction bit encodings, reverse the bit order
+ Target.reverseBitsForLittleEndianEncoding();
+
+ const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+ Target.getInstructionsByEnumValue();
+
+ // Emit function declaration
+ o << "uint64_t " << Target.getName();
+ o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
+ << " SmallVectorImpl<MCFixup> &Fixups,\n"
+ << " const MCSubtargetInfo &STI) const {\n";
+
+ // Emit instruction base values
+ o << " static const uint64_t InstBits[] = {\n";
+ for (std::vector<const CodeGenInstruction*>::const_iterator
+ IN = NumberedInstructions.begin(),
+ EN = NumberedInstructions.end();
+ IN != EN; ++IN) {
+ const CodeGenInstruction *CGI = *IN;
+ Record *R = CGI->TheDef;
+
+ if (R->getValueAsString("Namespace") == "TargetOpcode" ||
+ R->getValueAsBit("isPseudo")) {
+ o << " UINT64_C(0),\n";
+ continue;