+ class CodeGenInstruction {
+ public:
+ Record *TheDef; // The actual record defining this instruction.
+ std::string Namespace; // The namespace the instruction is in.
+
+ /// AsmString - The format string used to emit a .s file for the
+ /// instruction.
+ std::string AsmString;
+
+ /// Operands - This is information about the (ins) and (outs) list specified
+ /// to the instruction.
+ CGIOperandList Operands;
+
+ /// ImplicitDefs/ImplicitUses - These are lists of registers that are
+ /// implicitly defined and used by the instruction.
+ std::vector<Record*> ImplicitDefs, ImplicitUses;
+
+ // Various boolean values we track for the instruction.
+ bool isReturn : 1;
+ bool isBranch : 1;
+ bool isIndirectBranch : 1;
+ bool isCompare : 1;
+ bool isMoveImm : 1;
+ bool isBitcast : 1;
+ bool isSelect : 1;
+ bool isBarrier : 1;
+ bool isCall : 1;
+ bool canFoldAsLoad : 1;
+ bool mayLoad : 1;
+ bool mayLoad_Unset : 1;
+ bool mayStore : 1;
+ bool mayStore_Unset : 1;
+ bool isPredicable : 1;
+ bool isConvertibleToThreeAddress : 1;
+ bool isCommutable : 1;
+ bool isTerminator : 1;
+ bool isReMaterializable : 1;
+ bool hasDelaySlot : 1;
+ bool usesCustomInserter : 1;
+ bool hasPostISelHook : 1;
+ bool hasCtrlDep : 1;
+ bool isNotDuplicable : 1;
+ bool hasSideEffects : 1;
+ bool hasSideEffects_Unset : 1;
+ bool neverHasSideEffects : 1;
+ bool isAsCheapAsAMove : 1;
+ bool hasExtraSrcRegAllocReq : 1;
+ bool hasExtraDefRegAllocReq : 1;
+ bool isCodeGenOnly : 1;
+ bool isPseudo : 1;
+ bool isRegSequence : 1;
+ bool isExtractSubreg : 1;
+ bool isInsertSubreg : 1;
+
+ std::string DeprecatedReason;
+ bool HasComplexDeprecationPredicate;
+
+ /// Are there any undefined flags?
+ bool hasUndefFlags() const {
+ return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset;
+ }
+
+ // The record used to infer instruction flags, or NULL if no flag values
+ // have been inferred.
+ Record *InferredFrom;
+
+ CodeGenInstruction(Record *R);
+
+ /// HasOneImplicitDefWithKnownVT - If the instruction has at least one
+ /// implicit def and it has a known VT, return the VT, otherwise return
+ /// MVT::Other.
+ MVT::SimpleValueType
+ HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const;
+
+
+ /// FlattenAsmStringVariants - Flatten the specified AsmString to only
+ /// include text from the specified variant, returning the new string.
+ static std::string FlattenAsmStringVariants(StringRef AsmString,
+ unsigned Variant);
+ };
+
+
+ /// CodeGenInstAlias - This represents an InstAlias definition.
+ class CodeGenInstAlias {
+ public:
+ Record *TheDef; // The actual record defining this InstAlias.
+
+ /// AsmString - The format string used to emit a .s file for the
+ /// instruction.
+ std::string AsmString;
+
+ /// Result - The result instruction.
+ DagInit *Result;
+
+ /// ResultInst - The instruction generated by the alias (decoded from
+ /// Result).
+ CodeGenInstruction *ResultInst;
+
+
+ struct ResultOperand {
+ private:
+ std::string Name;
+ Record *R;
+
+ int64_t Imm;
+ public:
+ enum {
+ K_Record,
+ K_Imm,
+ K_Reg
+ } Kind;
+
+ ResultOperand(std::string N, Record *r) : Name(N), R(r), Kind(K_Record) {}
+ ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
+ ResultOperand(Record *r) : R(r), Kind(K_Reg) {}
+
+ bool isRecord() const { return Kind == K_Record; }
+ bool isImm() const { return Kind == K_Imm; }
+ bool isReg() const { return Kind == K_Reg; }
+
+ StringRef getName() const { assert(isRecord()); return Name; }
+ Record *getRecord() const { assert(isRecord()); return R; }
+ int64_t getImm() const { assert(isImm()); return Imm; }
+ Record *getRegister() const { assert(isReg()); return R; }
+
+ unsigned getMINumOperands() const;
+ };
+
+ /// ResultOperands - The decoded operands for the result instruction.
+ std::vector<ResultOperand> ResultOperands;
+
+ /// ResultInstOperandIndex - For each operand, this vector holds a pair of
+ /// indices to identify the corresponding operand in the result
+ /// instruction. The first index specifies the operand and the second
+ /// index specifies the suboperand. If there are no suboperands or if all
+ /// of them are matched by the operand, the second value should be -1.
+ std::vector<std::pair<unsigned, int> > ResultInstOperandIndex;
+
+ CodeGenInstAlias(Record *R, unsigned Variant, CodeGenTarget &T);
+
+ bool tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo,
+ Record *InstOpRec, bool hasSubOps, ArrayRef<SMLoc> Loc,
+ CodeGenTarget &T, ResultOperand &ResOp);