+ unsigned getAsmParserVariantCount() const;
+
+ /// getAsmWriter - Return the AssemblyWriter definition for this target.
+ ///
+ Record *getAsmWriter() const;
+
+ /// getRegBank - Return the register bank description.
+ CodeGenRegBank &getRegBank() const;
+
+ /// getRegisterByName - If there is a register with the specific AsmName,
+ /// return it.
+ const CodeGenRegister *getRegisterByName(StringRef Name) const;
+
+ const std::vector<Record*> &getRegAltNameIndices() const {
+ if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
+ return RegAltNameIndices;
+ }
+
+ const CodeGenRegisterClass &getRegisterClass(Record *R) const {
+ return *getRegBank().getRegClass(R);
+ }
+
+ /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
+ /// specified physical register.
+ std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
+
+ ArrayRef<MVT::SimpleValueType> getLegalValueTypes() const {
+ if (LegalValueTypes.empty()) ReadLegalValueTypes();
+ return LegalValueTypes;
+ }
+
+ /// isLegalValueType - Return true if the specified value type is natively
+ /// supported by the target (i.e. there are registers that directly hold it).
+ bool isLegalValueType(MVT::SimpleValueType VT) const {
+ ArrayRef<MVT::SimpleValueType> LegalVTs = getLegalValueTypes();
+ for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
+ if (LegalVTs[i] == VT) return true;
+ return false;
+ }
+
+ CodeGenSchedModels &getSchedModels() const;
+
+private:
+ DenseMap<const Record*, CodeGenInstruction*> &getInstructions() const {