projects
/
oota-llvm.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Generalize the register matching code in DAGISel a bit.
[oota-llvm.git]
/
utils
/
TableGen
/
InstrEnumEmitter.cpp
diff --git
a/utils/TableGen/InstrEnumEmitter.cpp
b/utils/TableGen/InstrEnumEmitter.cpp
index d1e7f3dd35d66444cee5a73ac8e743f5ff68e569..aa596892f52f0916b45efc46086de6c079e2001d 100644
(file)
--- a/
utils/TableGen/InstrEnumEmitter.cpp
+++ b/
utils/TableGen/InstrEnumEmitter.cpp
@@
-23,25
+23,18
@@
void InstrEnumEmitter::run(raw_ostream &OS) {
EmitSourceFileHeader("Target Instruction Enum Values", OS);
OS << "namespace llvm {\n\n";
EmitSourceFileHeader("Target Instruction Enum Values", OS);
OS << "namespace llvm {\n\n";
- CodeGenTarget Target;
+ CodeGenTarget Target
(Records)
;
// We must emit the PHI opcode first...
// We must emit the PHI opcode first...
- std::string Namespace;
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II) {
- if (II->second.Namespace != "TargetOpcode") {
- Namespace = II->second.Namespace;
- break;
- }
- }
+ std::string Namespace = Target.getInstNamespace();
if (Namespace.empty()) {
fprintf(stderr, "No instructions defined!\n");
exit(1);
}
if (Namespace.empty()) {
fprintf(stderr, "No instructions defined!\n");
exit(1);
}
- std::vector<const CodeGenInstruction*> NumberedInstructions;
-
Target.getInstructionsByEnumValue(NumberedInstructions
);
+ const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+
Target.getInstructionsByEnumValue(
);
OS << "namespace " << Namespace << " {\n";
OS << " enum {\n";
OS << "namespace " << Namespace << " {\n";
OS << " enum {\n";