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Added support to have TableGen provide information if an intrinsic (core
[oota-llvm.git]
/
utils
/
TableGen
/
InstrInfoEmitter.h
diff --git
a/utils/TableGen/InstrInfoEmitter.h
b/utils/TableGen/InstrInfoEmitter.h
index b721adcf4cef36bce99e001f1dc2fd28ae6c1def..870ea0c58780963223570e35898f984e418c3cfa 100644
(file)
--- a/
utils/TableGen/InstrInfoEmitter.h
+++ b/
utils/TableGen/InstrInfoEmitter.h
@@
-41,13
+41,10
@@
public:
private:
typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
private:
typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
- // Instruction analysis.
- void InferFromPattern(const CodeGenInstruction &Inst,
- bool &isStore, bool &isLoad, bool &NeverHasSideEffects);
-
void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map<std::vector<Record*>, unsigned> &EL,
void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map<std::vector<Record*>, unsigned> &EL,
+ std::map<Record*, unsigned> &BM,
const OperandInfoMapTy &OpInfo,
std::ostream &OS);
void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
const OperandInfoMapTy &OpInfo,
std::ostream &OS);
void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
@@
-60,6
+57,10
@@
private:
// Operand information.
void EmitOperandInfo(std::ostream &OS, OperandInfoMapTy &OperandInfoIDs);
std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
// Operand information.
void EmitOperandInfo(std::ostream &OS, OperandInfoMapTy &OperandInfoIDs);
std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
+
+ void DetectRegisterClassBarriers(std::vector<Record*> &Defs,
+ const std::vector<CodeGenRegisterClass> &RCs,
+ std::vector<Record*> &Barriers);
};
} // End llvm namespace
};
} // End llvm namespace