- RegSeqs.add(SuperRegList);
-
- // The list of overlaps doesn't need to have any particular order, except
- // Reg itself must be the first element. Pick an ordering that has one of
- // the other lists as a suffix.
- RegVec &OverlapList = OverlapLists[i];
- const RegVec &Suffix = SubRegList.size() > SuperRegList.size() ?
- SubRegList : SuperRegList;
- CodeGenRegister::Set Omit(Suffix.begin(), Suffix.end());
-
- // First element is Reg itself.
- OverlapList.push_back(Reg);
- Omit.insert(Reg);
-
- // Any elements not in Suffix.
- const CodeGenRegister::Set &OSet = Overlaps[Reg];
- std::set_difference(OSet.begin(), OSet.end(),
- Omit.begin(), Omit.end(),
- std::back_inserter(OverlapList),
- CodeGenRegister::Less());
-
- // Finally, Suffix itself.
- OverlapList.insert(OverlapList.end(), Suffix.begin(), Suffix.end());
- RegSeqs.add(OverlapList);
+ diffEncode(SuperRegLists[i], Reg->EnumValue,
+ SuperRegList.begin(), SuperRegList.end());
+ DiffSeqs.add(SuperRegLists[i]);
+
+ // The list of overlaps doesn't need to have any particular order, and Reg
+ // itself must be omitted.
+ DiffVec &OverlapList = OverlapLists[i];
+ CodeGenRegister::Set OSet;
+ Reg->computeOverlaps(OSet, RegBank);
+ OSet.erase(Reg);
+ diffEncode(OverlapList, Reg->EnumValue, OSet.begin(), OSet.end());
+ DiffSeqs.add(OverlapList);
+
+ // Differentially encode the register unit list, seeded by register number.
+ // First compute a scale factor that allows more diff-lists to be reused:
+ //
+ // D0 -> (S0, S1)
+ // D1 -> (S2, S3)
+ //
+ // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
+ // value for the differential decoder is the register number multiplied by
+ // the scale.
+ //
+ // Check the neighboring registers for arithmetic progressions.
+ unsigned ScaleA = ~0u, ScaleB = ~0u;
+ ArrayRef<unsigned> RUs = Reg->getNativeRegUnits();
+ if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size())
+ ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front();
+ if (i+1 != Regs.size() &&
+ Regs[i+1]->getNativeRegUnits().size() == RUs.size())
+ ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front();
+ unsigned Scale = std::min(ScaleB, ScaleA);
+ // Default the scale to 0 if it can't be encoded in 4 bits.
+ if (Scale >= 16)
+ Scale = 0;
+ RegUnitInitScale[i] = Scale;
+ DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs));