// TableGen is a tool which can be used to build up a description of something,
// then invoke one or more "tablegen backends" to emit information about the
// description in some predefined format. In practice, this is used by the LLVM
// TableGen is a tool which can be used to build up a description of something,
// then invoke one or more "tablegen backends" to emit information about the
// description in some predefined format. In practice, this is used by the LLVM
"Generate a register info description"),
clEnumValN(GenRegisterHeader, "gen-register-desc-header",
"Generate a register info description header"),
"Generate a register info description"),
clEnumValN(GenRegisterHeader, "gen-register-desc-header",
"Generate a register info description header"),
+ clEnumValN(GenInstrEnums, "gen-instr-enums",
+ "Generate enum values for instructions"),
+ clEnumValN(GenInstrs, "gen-instr-desc",
+ "Generate instruction descriptions"),
+ clEnumValN(GenAsmWriter, "gen-asm-writer",
+ "Generate assembly writer"),
+ clEnumValN(GenInstrSelector, "gen-instr-selector",
+ "Generate an instruction selector"),
+ clEnumValN(GenDAGISel, "gen-dag-isel",
+ "Generate a DAG instruction selector"),
clEnumValN(PrintEnums, "print-enums",
"Print enum values for a class"),
clEnumValN(Parse, "parse",
"Interpret machine code (testing only)"),
clEnumValN(PrintEnums, "print-enums",
"Print enum values for a class"),
clEnumValN(Parse, "parse",
"Interpret machine code (testing only)"),
static Init *getBit(Record *R, unsigned BitNo) {
const std::vector<RecordVal> &V = R->getValues();
for (unsigned i = 0, e = V.size(); i != e; ++i)
if (V[i].getPrefix()) {
assert(dynamic_cast<BitsInit*>(V[i].getValue()) &&
static Init *getBit(Record *R, unsigned BitNo) {
const std::vector<RecordVal> &V = R->getValues();
for (unsigned i = 0, e = V.size(); i != e; ++i)
if (V[i].getPrefix()) {
assert(dynamic_cast<BitsInit*>(V[i].getValue()) &&
- unsigned FirstFixedBit, unsigned MaxBits,
- unsigned &FirstVaryingBitOverall,
- unsigned &LastFixedBitOverall) {
+ unsigned FirstFixedBit, unsigned MaxBits,
+ unsigned &FirstVaryingBitOverall,
+ unsigned &LastFixedBitOverall) {
unsigned LastFixedBit = FirstVaryingBit;
while (LastFixedBit < MaxBits && BitsAreFixed(I1, I2, LastFixedBit))
++LastFixedBit;
unsigned LastFixedBit = FirstVaryingBit;
while (LastFixedBit < MaxBits && BitsAreFixed(I1, I2, LastFixedBit))
++LastFixedBit;
if (FirstVaryingBit < FirstVaryingBitOverall)
FirstVaryingBitOverall = FirstVaryingBit;
if (LastFixedBit < LastFixedBitOverall)
if (FirstVaryingBit < FirstVaryingBitOverall)
FirstVaryingBitOverall = FirstVaryingBit;
if (LastFixedBit < LastFixedBitOverall)
for (unsigned i = BitBegin; i != BitEnd; ++i) {
bool V1 = getBitValue(R1, i), V2 = getBitValue(R2, i);
if (V1 < V2)
for (unsigned i = BitBegin; i != BitEnd; ++i) {
bool V1 = getBitValue(R1, i), V2 = getBitValue(R2, i);
if (V1 < V2)
unsigned FirstFixedBit = 0;
for (std::vector<Record*>::iterator I = IB; I != IE; ++I)
FirstFixedBit = std::max(FirstFixedBit, getFirstFixedBit(*I, StartBit));
unsigned FirstFixedBit = 0;
for (std::vector<Record*>::iterator I = IB; I != IE; ++I)
FirstFixedBit = std::max(FirstFixedBit, getFirstFixedBit(*I, StartBit));
-// intentially taken by-copy) in half, narrowing down the possible instructions
-// that we may have found. Eventually, this list will get pared down to zero or
-// one instruction, in which case we have a match or failure.
+// intentionally taken by-copy) in half, narrowing down the possible
+// instructions that we may have found. Eventually, this list will get pared
+// down to zero or one instruction, in which case we have a match or failure.
-static Record *ParseMachineCode(std::vector<Record*>::iterator InstsB,
- std::vector<Record*>::iterator InstsE,
- unsigned char *M) {
+static Record *ParseMachineCode(std::vector<Record*>::iterator InstsB,
+ std::vector<Record*>::iterator InstsE,
+ unsigned char *M) {
assert(InstsB != InstsE && "Empty range?");
if (InstsB+1 == InstsE) {
// Only a single instruction, see if we match it...
Record *Inst = *InstsB;
for (unsigned i = 0, e = getNumBits(Inst); i != e; ++i)
if (BitInit *BI = dynamic_cast<BitInit*>(getBit(Inst, i)))
assert(InstsB != InstsE && "Empty range?");
if (InstsB+1 == InstsE) {
// Only a single instruction, see if we match it...
Record *Inst = *InstsB;
for (unsigned i = 0, e = getNumBits(Inst); i != e; ++i)
if (BitInit *BI = dynamic_cast<BitInit*>(getBit(Inst, i)))
LastFixedBit = ~0;
for (std::vector<Record*>::iterator I = InstsB+1; I != InstsE; ++I)
FindInstDifferences(*InstsB, *I, FirstFixedBit, MaxBits,
LastFixedBit = ~0;
for (std::vector<Record*>::iterator I = InstsB+1; I != InstsE; ++I)
FindInstDifferences(*InstsB, *I, FirstFixedBit, MaxBits,
while (RangeEnd != InstsE &&
BitRangesEqual(*RangeBegin, *RangeEnd, FirstVaryingBit, LastFixedBit))
++RangeEnd;
while (RangeEnd != InstsE &&
BitRangesEqual(*RangeBegin, *RangeEnd, FirstVaryingBit, LastFixedBit))
++RangeEnd;
// We just identified a range of equal instructions. If this range is the
// input range, we were not able to distinguish between the instructions in
// the set. Print an error and exit!
// We just identified a range of equal instructions. If this range is the
// input range, we were not able to distinguish between the instructions in
// the set. Print an error and exit!
if (RangeBegin == InstsB && RangeEnd == InstsE) {
std::cerr << "Error: Could not distinguish among the following insts!:\n";
PrintRange(InstsB, InstsE);
if (RangeBegin == InstsB && RangeEnd == InstsE) {
std::cerr << "Error: Could not distinguish among the following insts!:\n";
PrintRange(InstsB, InstsE);
static void PrintValue(Record *I, unsigned char *Ptr, const RecordVal &Val) {
assert(dynamic_cast<BitsInit*>(Val.getValue()) &&
static void PrintValue(Record *I, unsigned char *Ptr, const RecordVal &Val) {
assert(dynamic_cast<BitsInit*>(Val.getValue()) &&
for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i)
if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(i)))
Value |= B->getValue() << i;
for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i)
if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(i)))
Value |= B->getValue() << i;
- // Read the bits directly now...
- for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i)
- Value |= getMemoryBit(Ptr, Offset+i) << i;
- break;
+ // Read the bits directly now...
+ for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i)
+ Value |= getMemoryBit(Ptr, Offset+i) << i;
+ break;
TypedInit *TI = VBI->getVariable();
if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
if (VI->getName() == Val.getName())
TypedInit *TI = VBI->getVariable();
if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
if (VI->getName() == Val.getName())
const std::vector<RecordVal> &Vals = I->getValues();
for (unsigned i = 0, e = Vals.size(); i != e; ++i)
if (!Vals[i].getValue()->isComplete()) {
const std::vector<RecordVal> &Vals = I->getValues();
for (unsigned i = 0, e = Vals.size(); i != e; ++i)
if (!Vals[i].getValue()->isComplete()) {
- 0x89, 0xE5, // mov EBP, ESP
- //0x83, 0xEC, 0x08, // sub ESP, 0x8
- 0xE8, 1, 2, 3, 4, // call +0x04030201
- 0x89, 0xEC, // mov ESP, EBP
- 0x5D, // pop EBP
- 0xC3, // ret
- 0x90, // nop
- 0xC9, // leave
- 0x89, 0xF6, // mov ESI, ESI
- 0x68, 1, 2, 3, 4, // push 0x04030201
- 0x5e, // pop ESI
- 0xFF, 0xD0, // call EAX
- 0xB8, 1, 2, 3, 4, // mov EAX, 0x04030201
- 0x85, 0xC0, // test EAX, EAX
- 0xF4, // hlt
+ 0x89, 0xE5, // mov EBP, ESP
+ //0x83, 0xEC, 0x08, // sub ESP, 0x8
+ 0xE8, 1, 2, 3, 4, // call +0x04030201
+ 0x89, 0xEC, // mov ESP, EBP
+ 0x5D, // pop EBP
+ 0xC3, // ret
+ 0x90, // nop
+ 0xC9, // leave
+ 0x89, 0xF6, // mov ESI, ESI
+ 0x68, 1, 2, 3, 4, // push 0x04030201
+ 0x5e, // pop ESI
+ 0xFF, 0xD0, // call EAX
+ 0xB8, 1, 2, 3, 4, // mov EAX, 0x04030201
+ 0x85, 0xC0, // test EAX, EAX
+ 0xF4, // hlt
- unsigned char Buffer[] = { 0xbf, 0xe0, 0x20, 0x1f, 0x1, 0x0, 0x0, 0x1,
+ unsigned char Buffer[] = { 0xbf, 0xe0, 0x20, 0x1f, 0x1, 0x0, 0x0, 0x1,
0x0, 0x0, 0x0, 0x0, 0xc1, 0x0, 0x20, 0x1, 0x1,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x1,
0x0, 0x0, 0x0, 0x0, 0xc1, 0x0, 0x20, 0x1, 0x1,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x1,