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Remove stray comma in enum to satisfy -Wpedantic.
[oota-llvm.git]
/
utils
/
TableGen
/
X86RecognizableInstr.cpp
diff --git
a/utils/TableGen/X86RecognizableInstr.cpp
b/utils/TableGen/X86RecognizableInstr.cpp
index c360d866fa700a6de49fc26de7fcd693baab5fbb..17fd0ec5c6efa617c6a941011eccef86e3e5c8cc 100644
(file)
--- a/
utils/TableGen/X86RecognizableInstr.cpp
+++ b/
utils/TableGen/X86RecognizableInstr.cpp
@@
-80,7
+80,7
@@
namespace X86Local {
XD = 11, XS = 12,
T8 = 13, P_TA = 14,
A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
XD = 11, XS = 12,
T8 = 13, P_TA = 14,
A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
- XOP8 = 20, XOP9 = 21, XOPA = 22
+ XOP8 = 20, XOP9 = 21, XOPA = 22
, PD = 23, T8PD = 24, TAPD = 25
};
}
};
}
@@
-230,7
+230,6
@@
RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
Prefix = byteFromRec(Rec, "Prefix");
Opcode = byteFromRec(Rec, "Opcode");
Form = byteFromRec(Rec, "FormBits");
Prefix = byteFromRec(Rec, "Prefix");
Opcode = byteFromRec(Rec, "Opcode");
Form = byteFromRec(Rec, "FormBits");
- SegOvr = byteFromRec(Rec, "SegOvrBits");
HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
@@
-255,7
+254,9
@@
RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
Operands = &insn.Operands.OperandList;
Operands = &insn.Operands.OperandList;
- IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
+ IsSSE = ((HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
+ (Name.find("16") == Name.npos)) ||
(Name.find("CRC32") != Name.npos);
HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
(Name.find("CRC32") != Name.npos);
HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
@@
-310,7
+311,7
@@
InstructionContext RecognizableInstr::insnContext() const {
}
// VEX_L & VEX_W
if (HasVEX_LPrefix && HasVEX_WPrefix) {
}
// VEX_L & VEX_W
if (HasVEX_LPrefix && HasVEX_WPrefix) {
- if (HasOpSizePrefix)
+ if (HasOpSizePrefix
|| Prefix == X86Local::PD
)
insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L_W_XS);
insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L_W_XS);
@@
-321,7
+322,8
@@
InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB(IC_EVEX_L_W);
} else if (HasVEX_LPrefix) {
// VEX_L
insnContext = EVEX_KB(IC_EVEX_L_W);
} else if (HasVEX_LPrefix) {
// VEX_L
- if (HasOpSizePrefix)
+ if (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L_XS);
insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L_XS);
@@
-333,7
+335,8
@@
InstructionContext RecognizableInstr::insnContext() const {
}
else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
// EVEX_L2 & VEX_W
}
else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
// EVEX_L2 & VEX_W
- if (HasOpSizePrefix)
+ if (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
@@
-344,10
+347,11
@@
InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB(IC_EVEX_L2_W);
} else if (HasEVEX_L2Prefix) {
// EVEX_L2
insnContext = EVEX_KB(IC_EVEX_L2_W);
} else if (HasEVEX_L2Prefix) {
// EVEX_L2
- if (HasOpSizePrefix)
+ if (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
- Prefix == X86Local::TAXD)
+
Prefix == X86Local::TAXD)
insnContext = EVEX_KB(IC_EVEX_L2_XD);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L2_XS);
insnContext = EVEX_KB(IC_EVEX_L2_XD);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L2_XS);
@@
-356,7
+360,8
@@
InstructionContext RecognizableInstr::insnContext() const {
}
else if (HasVEX_WPrefix) {
// VEX_W
}
else if (HasVEX_WPrefix) {
// VEX_W
- if (HasOpSizePrefix)
+ if (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_W_XS);
insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_W_XS);
@@
-367,7
+372,8
@@
InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB(IC_EVEX_W);
}
// No L, no W
insnContext = EVEX_KB(IC_EVEX_W);
}
// No L, no W
- else if (HasOpSizePrefix)
+ else if (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_OPSIZE);
else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
Prefix == X86Local::TAXD)
insnContext = EVEX_KB(IC_EVEX_OPSIZE);
else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
Prefix == X86Local::TAXD)
@@
-379,7
+385,8
@@
InstructionContext RecognizableInstr::insnContext() const {
/// eof EVEX
} else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
if (HasVEX_LPrefix && HasVEX_WPrefix) {
/// eof EVEX
} else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
if (HasVEX_LPrefix && HasVEX_WPrefix) {
- if (HasOpSizePrefix)
+ if (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = IC_VEX_L_W_OPSIZE;
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = IC_VEX_L_W_XS;
insnContext = IC_VEX_L_W_OPSIZE;
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = IC_VEX_L_W_XS;
@@
-388,11
+395,16
@@
InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_VEX_L_W_XD;
else
insnContext = IC_VEX_L_W;
insnContext = IC_VEX_L_W_XD;
else
insnContext = IC_VEX_L_W;
- } else if (HasOpSizePrefix && HasVEX_LPrefix)
+ } else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
+ HasVEX_LPrefix)
insnContext = IC_VEX_L_OPSIZE;
insnContext = IC_VEX_L_OPSIZE;
- else if (HasOpSizePrefix && HasVEX_WPrefix)
+ else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
+ HasVEX_WPrefix)
insnContext = IC_VEX_W_OPSIZE;
insnContext = IC_VEX_W_OPSIZE;
- else if (HasOpSizePrefix)
+ else if (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = IC_VEX_OPSIZE;
else if (HasVEX_LPrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_VEX_OPSIZE;
else if (HasVEX_LPrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
@@
-420,7
+432,8
@@
InstructionContext RecognizableInstr::insnContext() const {
else
insnContext = IC_VEX;
} else if (Is64Bit || HasREX_WPrefix) {
else
insnContext = IC_VEX;
} else if (Is64Bit || HasREX_WPrefix) {
- if (HasREX_WPrefix && HasOpSizePrefix)
+ if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
insnContext = IC_64BIT_REXW_OPSIZE;
else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
Prefix == X86Local::T8XD ||
insnContext = IC_64BIT_REXW_OPSIZE;
else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
Prefix == X86Local::T8XD ||
@@
-429,7
+442,8
@@
InstructionContext RecognizableInstr::insnContext() const {
else if (HasOpSizePrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_64BIT_XS_OPSIZE;
else if (HasOpSizePrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_64BIT_XS_OPSIZE;
- else if (HasOpSizePrefix)
+ else if (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = IC_64BIT_OPSIZE;
else if (HasAdSizePrefix)
insnContext = IC_64BIT_ADSIZE;
insnContext = IC_64BIT_OPSIZE;
else if (HasAdSizePrefix)
insnContext = IC_64BIT_ADSIZE;
@@
-457,7
+471,10
@@
InstructionContext RecognizableInstr::insnContext() const {
else if (HasOpSizePrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_XS_OPSIZE;
else if (HasOpSizePrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_XS_OPSIZE;
- else if (HasOpSizePrefix)
+ else if (HasOpSizePrefix && HasAdSizePrefix)
+ insnContext = IC_OPSIZE_ADSIZE;
+ else if (HasOpSizePrefix || Prefix == X86Local::PD ||
+ Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = IC_OPSIZE;
else if (HasAdSizePrefix)
insnContext = IC_ADSIZE;
insnContext = IC_OPSIZE;
else if (HasAdSizePrefix)
insnContext = IC_ADSIZE;
@@
-490,12
+507,6
@@
RecognizableInstr::filter_ret RecognizableInstr::filter() const {
// Filter out artificial instructions but leave in the LOCK_PREFIX so it is
// printed as a separate "instruction".
// Filter out artificial instructions but leave in the LOCK_PREFIX so it is
// printed as a separate "instruction".
- // Filter out instructions with segment override prefixes.
- // They're too messy to handle now and we'll special case them if needed.
-
- if (SegOvr)
- return FILTER_STRONG;
-
/////////////////
// FILTER_WEAK
/////////////////
// FILTER_WEAK
@@
-509,9
+520,7
@@
RecognizableInstr::filter_ret RecognizableInstr::filter() const {
// Special cases.
// Special cases.
- if (Name == "MOVPQI2QImr" ||
- Name == "VMOVPQI2QImr" ||
- Name == "VMASKMOVDQU64")
+ if (Name == "VMASKMOVDQU64")
return FILTER_WEAK;
// XACQUIRE and XRELEASE reuse REPNE and REP respectively.
return FILTER_WEAK;
// XACQUIRE and XRELEASE reuse REPNE and REP respectively.
@@
-858,7
+867,8
@@
void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
switch (Prefix) {
default: llvm_unreachable("Invalid prefix!");
switch (Prefix) {
default: llvm_unreachable("Invalid prefix!");
- // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
+ // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
+ case X86Local::PD:
case X86Local::XD:
case X86Local::XS:
case X86Local::TB:
case X86Local::XD:
case X86Local::XS:
case X86Local::TB:
@@
-904,6
+914,7
@@
void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
opcodeToSet = Opcode;
break;
case X86Local::T8:
opcodeToSet = Opcode;
break;
case X86Local::T8:
+ case X86Local::T8PD:
case X86Local::T8XD:
case X86Local::T8XS:
opcodeType = THREEBYTE_38;
case X86Local::T8XD:
case X86Local::T8XS:
opcodeType = THREEBYTE_38;
@@
-947,6
+958,7
@@
void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
opcodeToSet = Opcode;
break;
case X86Local::P_TA:
opcodeToSet = Opcode;
break;
case X86Local::P_TA:
+ case X86Local::TAPD:
case X86Local::TAXD:
opcodeType = THREEBYTE_3A;
if (needsModRMForDecode(Form))
case X86Local::TAXD:
opcodeType = THREEBYTE_3A;
if (needsModRMForDecode(Form))