Merge tag 'v3.17-rockchip-rk3288' of git://git.kernel.org/pub/scm/linux/kernel/git...

[firefly-linux-kernel-4.4.55.git] / Documentation / devicetree / bindings / arm / exynos / power_domain.txt

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b419016aa7065e618285047b44ab0b033e1e..8b4f7b7fe88b9fc181b41e4a6eb68406dd6094d3 100644 (file)
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -9,6 +9,18 @@ Required Properties:
 - reg: physical base address of the controller and length of memory mapped
     region.
 
+Optional Properties:
+- clocks: List of clock handles. The parent clocks of the input clocks to the
+       devices in this power domain are set to oscclk before power gating
+       and restored back after powering on a domain. This is required for
+       all domains which are powered on and off and not required for unused
+       domains.
+- clock-names: The following clocks can be specified:
+       - oscclk: Oscillator clock.
+       - pclkN, clkN: Pairs of parent of input clock and input clock to the
+               devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
+               are supported currently.
+
 Node of a device using power domains must have a samsung,power-domain property
 defined with a phandle to respective power domain.
 
@@ -19,6 +31,14 @@ Example:
                reg = <0x10023C00 0x10>;
        };
 
+       mfc_pd: power-domain@10044060 {
+               compatible = "samsung,exynos4210-pd";
+               reg = <0x10044060 0x20>;
+               clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+                       <&clock CLK_MOUT_USER_ACLK333>;
+               clock-names = "oscclk", "pclk0", "clk0";
+       };
+
 Example of the node using power domain:
 
        node {