KVM: PPC: e500: Add support for TLBnPS registers

[firefly-linux-kernel-4.4.55.git] / Documentation / virtual / kvm / api.txt

diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index 119358dfb74295af7e95c6ecdcda35e9cf1d8f17..f045377ae5a08b109684171f0d7efdbb34122ed6 100644 (file)
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -1486,15 +1486,23 @@ struct kvm_ioeventfd {
        __u8  pad[36];
 };
 
+For the special case of virtio-ccw devices on s390, the ioevent is matched
+to a subchannel/virtqueue tuple instead.
+
 The following flags are defined:
 
 #define KVM_IOEVENTFD_FLAG_DATAMATCH (1 << kvm_ioeventfd_flag_nr_datamatch)
 #define KVM_IOEVENTFD_FLAG_PIO       (1 << kvm_ioeventfd_flag_nr_pio)
 #define KVM_IOEVENTFD_FLAG_DEASSIGN  (1 << kvm_ioeventfd_flag_nr_deassign)
+#define KVM_IOEVENTFD_FLAG_VIRTIO_CCW_NOTIFY \
+       (1 << kvm_ioeventfd_flag_nr_virtio_ccw_notify)
 
 If datamatch flag is set, the event will be signaled only if the written value
 to the registered address is equal to datamatch in struct kvm_ioeventfd.
 
+For virtio-ccw devices, addr contains the subchannel id and datamatch the
+virtqueue index.
+
 
 4.60 KVM_DIRTY_TLB
 
@@ -1780,6 +1788,25 @@ registers, find a list below:
   PPC   | KVM_REG_PPC_VPA_DTL   | 128
   PPC   | KVM_REG_PPC_EPCR     | 32
   PPC   | KVM_REG_PPC_EPR      | 32
+  PPC   | KVM_REG_PPC_TCR      | 32
+  PPC   | KVM_REG_PPC_TSR      | 32
+  PPC   | KVM_REG_PPC_OR_TSR   | 32
+  PPC   | KVM_REG_PPC_CLEAR_TSR        | 32
+  PPC   | KVM_REG_PPC_MAS0     | 32
+  PPC   | KVM_REG_PPC_MAS1     | 32
+  PPC   | KVM_REG_PPC_MAS2     | 64
+  PPC   | KVM_REG_PPC_MAS7_3   | 64
+  PPC   | KVM_REG_PPC_MAS4     | 32
+  PPC   | KVM_REG_PPC_MAS6     | 32
+  PPC   | KVM_REG_PPC_MMUCFG   | 32
+  PPC   | KVM_REG_PPC_TLB0CFG  | 32
+  PPC   | KVM_REG_PPC_TLB1CFG  | 32
+  PPC   | KVM_REG_PPC_TLB2CFG  | 32
+  PPC   | KVM_REG_PPC_TLB3CFG  | 32
+  PPC   | KVM_REG_PPC_TLB0PS   | 32
+  PPC   | KVM_REG_PPC_TLB1PS   | 32
+  PPC   | KVM_REG_PPC_TLB2PS   | 32
+  PPC   | KVM_REG_PPC_TLB3PS   | 32
 
 ARM registers are mapped using the lower 32 bits.  The upper 16 of that
 is the register group type, or coprocessor number: