fix up a bug in multicore RAW interruption version codes

[IRC.git] / Robust / src / Runtime / raw_interrupt.s

diff --git a/Robust/src/Runtime/raw_interrupt.s b/Robust/src/Runtime/raw_interrupt.s
index 1581b4e46b88a0033918ed39c967b6ff248c0e35..2498ff50e66a80c9e6d32f88b5db0d14b627d856 100644 (file)
--- a/Robust/src/Runtime/raw_interrupt.s
+++ b/Robust/src/Runtime/raw_interrupt.s
@@ -1,38 +1,18 @@
 #include <raw_asm.h>
 
-       .text
+.text
        .align  2
        .globl  setup_ints
        .ent    setup_ints
 setup_ints:    
-       # run main program
-       # set up switch
-#      mtsri   SW_FREEZE, 1
-#      la      $8, __sw_main
-#      mtsr    SW_PC, $8
-#      nop
-#      mtsri   SW_FREEZE, 0
-       
        # set up dynamic network
        uintoff
        intoff
 
        # set gdn_cfg
-#   la $8, ((XSIZE-1)<<27)|((YSIZE-1)<<22)|(XOFF<<17)|(YOFF<<12)|(LOG_XSIZE<<9)
        xor $8,$8,$8
-#ifdef Y1
        aui $8,$8,(3<<11)|(0 <<6)|(0 <<1)
        ori $8, (0 <<12)|(2<<9)
-#elif defined Y2
-       aui $8,$8,(3<<11)|(1 <<6)|(0 <<1)
-       ori $8, (0 <<12)|(2<<9)
-#elif defined Y4
-       aui $8,$8,(3<<11)|(3 <<6)|(0 <<1)
-       ori $8, (0 <<12)|(2<<9)
-#else
-       aui $8,$8,(3<<11)|(3 <<6)|(0 <<1)
-       ori $8, (0 <<12)|(2<<9)
-#endif
        mtsr    GDN_CFG,$8
 #      mtsr    PASS,$8
 
@@ -49,10 +29,9 @@ setup_ints:
 
        inton
        uinton
-
+       jr $31
        .end    setup_ints
 
-
 .macro empty_vec fail_code
         mtsri FAIL, \fail_code
 1:      b 1b
@@ -73,10 +52,48 @@ vec_extern:
 vec_timer:
         empty_vec 0x2304
 vec_gdn_avail:
-       sw      $2,-8($sp)
-#      la      $2,gdn_avail_handler
-#      jr      $2
-       jal recvMsg 
+       mtsri PASS, 0xef00
+       uintoff
+
+       addiu   $sp,$sp,-64
+       sw      $31,0x3c($sp)
+       sw      $30,0x38($sp)
+       sw      $23,0x34($sp)
+       sw      $22,0x30($sp)
+       sw      $21,0x2c($sp)
+       sw      $20,0x28($sp)
+       sw      $19,0x24($sp)
+       sw      $18,0x20($sp)
+       sw      $17,0x1c($sp)
+       sw      $16,0x18($sp)
+       sw      $7,0x14($sp)
+       sw      $6,0x10($sp)
+       sw      $5,0xc($sp)
+       sw      $4,0x8($sp)
+       sw      $3,0x4($sp)
+       sw      $2,0x0($sp)
+
+       jal receiveObject
+
+       lw      $31,0x3c($sp)
+       lw      $30,0x38($sp)
+       lw      $23,0x34($sp)
+       lw      $22,0x30($sp)
+       lw      $21,0x2c($sp)
+       lw      $20,0x28($sp)
+       lw      $19,0x24($sp)
+       lw      $18,0x20($sp)
+       lw      $17,0x1c($sp)
+       lw      $16,0x18($sp)
+       lw      $7,0x14($sp)
+       lw      $6,0x10($sp)
+       lw      $5,0xc($sp)
+       lw      $4,0x8($sp)
+       lw      $3,0x4($sp)
+       lw      $2,0x0($sp)
+       addiu   $sp,$sp,64
+
+       mtsri PASS, 0xefff
+       dret
 vec_event_counters:
         empty_vec 0x2306
-