ARC: cacheflush refactor #2: I and D caches lines to have same size

[firefly-linux-kernel-4.4.55.git] / arch / arc / include / asm / cache.h

diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index e4abdaac6f9fead2fc27807602090937d20addae..2fd3162ec4df13db67b8ba62bc4a6d7e9a603763 100644 (file)
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -17,13 +17,7 @@
 #endif
 
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
-
-/* For a rare case where customers have differently config I/D */
-#define ARC_ICACHE_LINE_LEN    L1_CACHE_BYTES
-#define ARC_DCACHE_LINE_LEN    L1_CACHE_BYTES
-
-#define ICACHE_LINE_MASK       (~(ARC_ICACHE_LINE_LEN - 1))
-#define DCACHE_LINE_MASK       (~(ARC_DCACHE_LINE_LEN - 1))
+#define CACHE_LINE_MASK                (~(L1_CACHE_BYTES - 1))
 
 /*
  * ARC700 doesn't cache any access in top 256M.